Nonvolatile memory cell, operating method of the same and nonvolatile memory array

ABSTRACT

The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array.  
     A p-well  101  is formed in a surface of a substrate  10  and a channel forming semiconductor region  110  is defined in a surface of the p-well  101  and separated by a first n +  region  121  and a second n +  region  122.  A carrier-supplying portion (CS: carrier supply)  111  is formed coming into contact with the first n +  region  121  and a carrier-acceleration-injection portion  112  (AI: acceleration and injection) is in contact with the second n +  region  122  in the channel forming semiconductor region  110  wherein the carrier-supplying portion  111  and carrier-acceleration-injection portion  112  are in contact with each other.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a nonvolatile memory cell, anonvolatile memory array and a method of operating the same, and moreparticularly to a nonvolatile memory cell and/or array and a method ofoperating the same enabling high integration density, low voltageprogramming and/or high speed programming.

[0003] A MNOS memory is one of typical semiconductor memories whereincarrier charge is stored in a gate insulator to have informationnonvolatilely stored. The MNOS memory is of a laminated structurecomprising a conductive gate (M), a silicon nitride film (N), a tunneloxide film (O) and a semiconductor wherein the carrier (electron orhole) is captured at a trapping level in the silicon nitride film tostore the carrier charge. In this step, the silicon nitride film of theMNOS memory was required to be more than 19 nm in thickness since thecharge trapping efficiency depended on the carrier capture distance inthe silicon nitride film (Document 1: F. L. Hampton and J. R. Cricchi“Space charge distribution limitation of scale down of MNOS devices”,1979 IEDM Technical Digest, p. 374).

[0004] To program (write or erase) the MNOS memory, at least more than10V or about 20V as a normal value of programming voltage was requiredfor a electric field to be fed to a semiconductor surface via thesilicon nitride film so that a carrier may be injected in the nitridefilm through (via a tunnel) the tunnel oxide film.

[0005] Also, a MONOS memory is disclosed as the nonvolatile memorycapable of reducing the programming voltage (Document 2: E. Suzuki, H.Hiraishi, K. Ishii and Y. Hayashi, “A Low-Voltage Alterable EEPROM withMetal-Oxide-nitride-Oxide and semiconductor (MONOS). Structures”, IEEETransaction on Election Devices, Vol. ED-30, February 1983, p. 122).This MONOS memory is of a laminated structure comprising a conductivegate (M), a top oxide film (O), a silicon nitride film (N), a tunneloxide film (O) and semiconductor. This structure has enabled the MONOSmemory to stop hopping via the carrier trapping level in the siliconnitride film due to a potential barrier formed between the nitride filmand the top oxide film, which resulted in making the nitride film asthin as possible. Further, carrier traps newly generated at theinterface between the top oxide film and nitride film has enlarged amemory window to the extent it is possible to identify the storedinformation even if the entire insulator thickness is made thinner.

[0006] This MONOS memory has made it possible to reduce the programmingvoltage down to 9V with the usable programming speed (0.1 msec) underthe condition that the stored information is maintained for tenyears(Document 3: T. Nozaki, T. Tanaka, Y. Kijiya, E. Kinoshita, T.Tsuchiya and Y. Hayashi, “A1-Mb EEPROM with MONOS Memory Cell forSemiconductor Disk Application”, IEEE Journal of Solid-State Circuits,Vol.26, No.4, April, 1991, p.497).

[0007] It has yet to be disclosed, however, whether or not it ispossible to reduce a programming voltage to be less than 9V under thecondition that the programming speed is less than 0.1 mscc and memoryretention characteristics are maintained. To achieve the programmingvoltage of less than 9V, either programming speed or memory storagecharacteristics or both were required to be sacrificed.

[0008] Disclosed is a technology to integrate a single transistor cellwith a single gate (to be connected to a word line) in the form of anarray to improve integration density which is more excellent than thatdisclosed in the Document 3 as described above. However, since it wasrequired to supply electrical potential to not only a drain region butalso a source region so as not to write in an unselected cell whichresults in separately connecting both drain and source regions to a bitline direction, it was impossible to improve the integration densityeven if a single gate structured single transistor cell is used therein.(Document 4: I. Fujiwara, H. Aozasa, A. Nakamura, Y. Komatsu, and Y.Hayashi, “0.13 μm MONOS single transistor memory cell with separatedsource”, 1998 IEDM Technical Digest, 36.7, p995-998, FIGS. 2 & 11).

[0009] When integrating a single gate cell in the form of an array toread the stored information, there is deterioration of memory retentioncharacteristics called “read disturb” since electrical potential forreading the stored information is to be supplied to a gate.

[0010] To prevent the deterioration of the retention characteristics asdescribed above and to keep the stored information well trapped even inthe state of electrical potential being supplied to a gate, it wasrequired to increase the thickness of the above-indicated tunnel oxidefilm from 2.0 nm to 2.7 nm. To make as minimal as possible theprogramming speed deterioration due to the increase of a tunnel oxidefilm thickness, it was necessary to increase programming voltage from 9Vto 12 V.

[0011] Meanwhile, disclosed is technology of ballistic carrier injectionfor a floating gate memory cell which is intended to enable reduction ofprogramming voltage and increase of programming speed (Document 5: S.Ogura, A. Hori, J. Kato, M. Yamanaka, S. Odanaka, H. Fujimoto, K.Akamatsu, T. Ogura, M. Komiya and H. Kotani, “Low voltage, Low current,High speed Program Step Split Gate Cell with Ballistic Direct Injectionfor EEPROM/Flash”, 1998 IEDM Technical Digest, 36.5, p.987-990). Theballistic carrier injection as described above has such a configurationthat formed in the form of a step in a surface of a semiconductorsubstrate is a thin drain region through which a hot carrier isballistically transported to a floating gate and the floating gate isdisposed to cover the step portion. This improves the injectionefficiency since the speed component in the carrier transport directioncontributes to generating energy for the carrier injection.

[0012] However, the carrier injection and discharge of a conventionalMONOS nonvolatile memory are carried out in an entire surface of achannel forming, a semiconductor region beneath a gate insulator inwhich carrier charge trapping function is incorporated and it was notknown from the carrier injection in a floating gate memory cell whetheror not current or voltage sensed at time of reading the memory cell wascontrolled by the carrier charge in the gate insulator trapped by localcarrier injection in source/drain directions in a channel formingsemiconductor region. Neither was it possible to clearly read that thecarrier charge injected through the above-mentioned thin drain resultedin changing current and voltage in the conventional MONOS nonvolatilememory.

[0013] With respect to a conventional floating gate memory, it is liableto cause defective bits if even one location of a gate insulator isfound to be defective which results in deteriorating the memoryretention characteristics of an entire cell. In addition, the ratio ofthe total capacitance of a floating gate to the capacitance between acontrol gate and floating gate decreases as a memory structure becomesfine. To eliminate the disadvantage as described above, it was requiredto adopt such a structure as to increase the overlapped area between thecontrol gate and floating gate and further, there was no choice but toincrease a number of manufacturing process steps and cell area.

SUMMARY OF THE INVENTION

[0014] It is a purpose of the present invention to resolve problems inthe conventional technology and provide a nonvolatile memory cell whichis not only capable of programming with lower voltage but also has aremote possibility of causing defective bits and has fewer manufacturingprocess steps compared to a conventional floating gate memory; a methodof using the same and a nonvolatile memory array.

[0015] To achieve the purpose as described above, the present inventionis provided with the means featured below:

[0016] A nonvolatile memory cell wherein first and second impurityregions of opposite conductivity type are formed in a main surface of asubstrate and separated therebetween by a channel forming semiconductorregion of one conductivity type in the main surface of the substrate anda gate electrode is formed on a gate insulator on the channel formingsemiconductor region, carriers being injected and stored in a carriertrapping means of the gate insulator further comprising:

[0017] (a) provided is an acceleration-electrical potential supplyingmeans to selectively supply the acceleration-electrical potential to oneout of the first and second impurity regions at one side;

[0018] (b) the channel forming semiconductor region includes acarrier-supplying portion and carrier-acceleration-injection portiondisposed along the carrier transport direction;

[0019] (c) the carrier-supplying portion supplies to thecarrier-acceleration-injection portion carriers supplied by the otherone out of the first and second impurity regions at the other side; and

[0020] (d) the carrier-acceleration-injection portion makes localinjection of carriers supplied from the carrier-supplying portion intothe gate insulator in the vicinity of the adjacent other one out offirst and second impurity regions at one side to which the acceleratedelectrical potential is supplied: and

[0021] (e) the gate insulator is provided with at least a carrier chargetrapping means in a projecting area of thecarrier-acceleration-injection portion.

[0022] According to the features as described above, a space chargeregion is extended from a second impurity region to acarrier-acceleration-injection portion by electric field due toelectrical potential supplied to a second impurity region. Out ofcarriers supplied to the carrier-acceleration-injection portion, energyis supplied by the electrical potential difference in the space chargeregion to a carrier which is moved as far as near the interface with thesecond impurity region without being affected by lattice scattering andthe aforesaid carrier is injected, that is, locally injected in a verynarrow region of the carrier charge trapping means getting over apotential barrier formed at the interface with the gate insulator.

[0023] More particularly, it is possible to supply to a carrier energygetting over the potential barrier V_(B) between a gate insulator andcarrier-acceleration injection portion with the distance three times themean free path of a high energy carrier by disposing acarrier-acceleration-injection portion in a channel formingsemiconductor region. The shorter the distance within which energy issupplied to a carrier (and which generates electrical potentialdifference of V_(B)), the more the carrier number getting over theelectrical potential increases. However, as the distance becomesshorter, probability of a carrier tunneling increases due to highelectric field and the lower limit of the distance is determined as avalue (near to the aforementioned three times the mean free path of ahigh energy carrier) to prevent the useless current increase due to theincrease of the carrier tunneling. If the distance within which theenergy is supplied to the carrier (which generates the electricalpotential difference of V_(B)) exceeds fourteen times the mean free pathof the high energy carrier, the injection efficiency is almost the sameas that of the conventional channel hot electron injection.

[0024] Meanwhile, it is possible to read the information trapped in acell by detecting a cell current or cell threshold voltage even if acarrier charge is not trapped in an entire region of a gate insulatorhaving carrier charge trapping function. For example, it is possible toread the information if the carrier charge is trapped in a length (tothe direction connecting a first impurity region and second impurityregion) of the gate insulator which is more than 20 nm long out of gateinsulators.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 shows a section of a nonvolatile memory cell in a firstembodiment of the present invention.

[0026]FIG. 2 shows an equivalent circuit of a nonvolatile memory cell inFIG. 1.

[0027]FIG. 3 shows a circuit configuration for a memory array in FIG. 1.

[0028]FIG. 4 shows a section of a nonvolatile memory cell in a thirdembodiment of the present invention.

[0029]FIG. 5 shows an equivalent circuit of a nonvolatile memory cell inFIG. 4.

[0030]FIG. 6 shows a circuit configuration (First embodiment) for amemory array in FIG. 4.

[0031]FIG. 7 shows a circuit configuration (Second embodiment) for amemory array in FIG. 4.

[0032]FIG. 8 is a signal waveform illustration showing a programming andreading method for a memory array in FIG. 4.

[0033]FIG. 9 shows a circuit configuration (Third embodiment) for amemory array in FIG. 4.

[0034]FIG. 10 shows a circuit configuration (Fourth embodiment) for amemory array in FIG. 4.

[0035]FIG. 11 shows a section of a nonvolatile memory cell in a fourthembodiment of the present invention.

[0036]FIG. 12 shows a section of a nonvolatile memory cell in a fifthembodiment of the present invention.

[0037]FIG. 13 shows a section of a nonvolatile memory cell in a sixthembodiment of the present invention.

[0038]FIG. 14 shows a section of a nonvolatile memory cell in a seventhembodiment of the present invention.

[0039]FIG. 15 shows an equivalent circuit of a nonvolatile memory cellin FIG. 14.

[0040]FIG. 16 shows a section of a nonvolatile memory cell in a eighthembodiment of the present invention.

[0041]FIG. 17 shows a section of a nonvolatile memory cell in a ninthembodiment of the present invention.

[0042]FIG. 18 shows a section of a nonvolatile memory cell in a tenthembodiment of the present invention.

[0043]FIG. 19 shows a section of a nonvolatile memory cell in a eleventhembodiment of the present invention.

[0044]FIG. 20 shows a section of a nonvolatile memory cell in a twelfthembodiment of the present invention.

[0045]FIG. 21 is an illustration showing a carrier injection in anembodiment of the present invention in FIG. 20.

[0046]FIG. 22 is an illustration showing the carrier injection by theconventional technology.

[0047]FIG. 23 is an illustration showing a circuit configuration (Firstembodiment) of a memory cell in FIG. 20.

[0048]FIG. 24 is an illustration showing a circuit configuration (Secondembodiment) of a memory cell in FIG. 20.

[0049]FIG. 25 is a signal waveform illustration showing a method ofprogramming, a memory cell in FIG. 20.

[0050]FIG. 26 is a signal waveform illustration showing a method ofreading a memory cell in FIG. 20.

[0051]FIG. 27 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (First embodiment) of it.

[0052]FIG. 28 is a sectional view of a nonvolatile memory cell in FIG.20 showing, a manufacturing method (Second embodiment) of it.

[0053]FIG. 29 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (Third embodiment) of it.

[0054]FIG. 30 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (fourth embodiment) of it.

[0055]FIG. 31 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (Fifth embodiment) of it.

[0056]FIG. 32 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (Sixth embodiment) of it.

[0057]FIG. 33 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (Seventh embodiment) of it.

[0058]FIG. 34 is a sectional view of a nonvolatile memory cell in FIG.20 showing a manufacturing method (Eighth embodiment) of it.

[0059]FIG. 35 shows a section of a nonvolatile memory cell in a secondembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] The detailed description of the present invention is now providedbelow in reference to the accompanying drawings. FIG. 1 shows a sectionof a nonvolatile memory cell in a first embodiment of the presentinvention and FIG. 2, an equivalent circuit thereto.

[0061] A p-well 101 is formed in a surface of a substrate 10 and achannel forming semiconductor region 110 is defined in a surface of thep-well 101 and separated by a first n⁺ region 121 (source/drain region:SD1)and a second n⁺ region 122(source/drain region: SD2). The channelforming semiconductor region 110 is a semiconductor region in a surfaceof which a channel is electrically induced and faded away and whichcomprises a surface of a semiconductor substrate itself or a wellsurface portion formed in a surface of a semiconductor substrate or asemiconductor thin film (SOI) formed on an insulating support substrate,etc. Thus, used as the substrate 10 are an SOI substrate and the likeformed in a semiconductor substrate or main surface thereof.

[0062] A carrier-supplying portion(CS: carrier supply)111 is formedcoming into contact with the first n⁺ region 121 and acarrier-acceleration-injection portion 112 (AI: acceleration andinjection) is in contact with the second n⁺ region 122 in said channelforming semiconductor region 110 wherein the carrier-supplying portion111 and carrier-acceleration-injection portion 112 are in contact witheach other.

[0063] The carrier-supplying portion 111 functions as a carrier path tosupply a carrier supplied from the first n⁺ region 121 to the channelforming semiconductor region 110 to the carrier-acceleration-injectionportion 112 through channels therein or in a surface thereof.

[0064] As described in detail hereinafter below, thecarrier-acceleration-injection portion 112 makes local injection of acarrier to which energy is supplied adjacent to the interface with thesecond n⁺ region 122 in a very narrow region of a gate insulator 132.

[0065] The gate insulator 132 is formed to cover each opposite endsurface of the first and second n⁺ regions 121 and 122 and the channelforming semiconductor region 110, and a gate electrode 140 is formed onthe gate insulator 132 to bridge each n⁺ region 121 and n⁺ region 122.

[0066] The gate insulator 132 is of a three-layer structure having acarrier trapping means. A first layer 132 a on the channel formingsemiconductor region 110 is preferably made from silicon oxide film(O)or silicon nitrided oxide film(ON), etc. forming a potential barrier atthe interface with the channel forming semiconductor region 110.

[0067] A second layer 132 b is preferably made from a silicon nitridefilm(N) or tantalum oxide film(T). It is also recommended thatparticulates of lower energy gap material such as TiN and the like, orof conductive material be buried in the silicon nitride film to improvethe trapping probability of the injected carrier(electron). In addition,it is desirable that the film thickness of the silicon nitride film beless than 10 nm to enable programming with low voltage, but it isconfirmed that carrier trapping, is possible with even 4 nm. The siliconnitride film for the second layer 132 b may contain a smaller quantityof oxygen in atomic percent compared to the silicon nitrided oxide filmfor the first layer 132 a and third layer 132 c(In this case as well asthe case where particulates are buried in the silicon nitride films, asilicon nitride film for the second layer is designated as siliconnitride film(N) to differentiate the silicon nitride film for the secondlayer from that of the first and third layer in this embodiment.)

[0068] The third layer 132 c beneath a gate electrode□(140) ispreferably made from a silicon oxide film(O) or silicon nitrided oxidefilm(ON) and the film thickness for both films is preferably more than 2nm. A carrier charge is captured and trapped by a carrier trap level ortrap site(carrier charge trapping function)formed within the secondlayer 132 b or at the interface with the second layer 132 b and thirdlayer 132 c.

[0069] It is possible to carry out the low voltage programming if thefirst layer 132 a is comprised of a silicon oxide film with thickness of3-4 nm or silicon nitrided oxide film and the third layer 132 ccomprises an oxide film with thickness of 2-4 nm or a silicon nitridedoxide film. Additionally, this makes the carrier tunnel probability ofthe third layer 132 c higher than that of the first layer 132 a and itis thus possible to make the electrical potential to be applied to thegate electrode 140 at the time of programming (programming electricalpotential) and the electrical potential to be applied to the gateelectrode 140 at the time of erasing (erasing electrical potential) tobe the same polarity.

[0070] It is generally required to supply to a gate electrode electricalpotential whose polarity is different depending on when programming anderasing are carried out. That is, if a carrier is assumed to beelectron, a positive electrical potential is applied to the electrode140 at the time of programming and a negative electrical potential issupplied to the electrode 140 at the time of erasing. However,additional circuit technology is required to generate the highelectrical potential with different polarities in LSI which results inincreasing the manufacturing cost. To this end, the present inventionachieves carrier injection(programming)and extraction(erase) only bysupplying to the gate electrode 140 the electrical potential with thesame polarity and different level.

[0071] In the step as described above, if a silicon oxide film is usedfor the first layer 132 a and a silicon nitrided oxide film is adoptedfor the third layer 132 c, a potential barrier between the second layer132 b and third layer 132 c viewed from the second layer 132 b againstthe silicon nitrided oxide film is low and thus, the carrier tunnelprobability across the third layer 132 c becomes larger than the carriertunnel probability across the first layer 132 a even if the filmthickness thereof is the same. It is also possible to make the thicknessof the third layer 132 c thinner than that of the first layer 132 a ifthe silicon nitrided oxide film is used for each layer.

[0072] Combinations of material for a three-layer structure (firstlayer/second layer/third layer) can be designated such as O/N/O, ON/N/O,ON/N/ON, O/N/ON, O/T/O, ON/T/O, ON/T/ON AND O/T/ON.

[0073] If the length of the gate electrode 140 is 0.25-0.35 micro-meter,it is preferable that the impurity concentration of a carrier-supplyingportion(p-type) be about 2E17 atm/cm³, the impurity concentration of acarrier-acceleration-injection portion 112, about 1E18 atm/cm³ and thelength of the carrier-acceleration-injection portion be about 80 nm.

[0074] It is preferable that each n⁺ region 121 and 122 is furnishedwith each n region 121 n and 122 n in contact with a channel formingsemiconductor region 110 whose length is 50-70 nm and whose impurityconcentration is 1-2E19 atm/cm³ and the impurity concentration of the n⁺regions other than the n regions 121 n and 122 n, is about 1E21 atm/cm³.The gate electrode 140 preferably comprises n-type polycrystal siliconor a two-layer structure of polysilicon and silicide (tungsten silicide,titanium silicide and cobalt silicide, etc.).

[0075] Next, a principle of operation disclosed in an embodiment of thepresent invention is now described below. When the predeterminedacceleration-electrical potential(more than V_(B)−2φ_(F2), which isdescribed below) is supplied to the n⁺ region 122, the electricalpotential difference more than the potential barrier V_(B) to the gateinsulator 132 is formed in a surface of thecarrier-acceleration-injection portion and energy capable of gettingover the electrical potential V_(B) is supplied to carriers in partwhich pass the portion(space charge region). A carrier is generallytransported to the direction of n⁺ region 122 and the carrier which isscattered by lattice scattering to the direction of a carrier chargetrapping means arrives at the carrier charge trapping means to betrapped getting over the potential barrier.

[0076] Meanwhile, in order to supply to many carriers energy more thanthe equivalent of the electrical potential V_(B), it is required to forman electrical potential difference exceeding the electrical potentialV_(B) within the short length in the carrier-acceleration injectionportion. However, this means that high electric field is required to beformed in a semiconductor. And, it is not possible to make shorter thanabout 30 nm the length to form the electrical potential differencecorresponding to the potential barrier between silicon add a siliconoxide film, taking into account that the direct tunneling is startedwith the electric field of 1E6V/cm if silicon is used. Considering thata mean free path Lo for a high energy carrier is about 10 nm and saidhigh electric field is formed on the portion corresponding to the lengthof 3Lo,out of the accelerated carriers, a carrier to be given the energycapable of getting over the potential barrier V_(B) is obtained at theratio of exp(−3Lo/Lo)=1/20. This is an adequately large value in view ofthe fact that the injection efficiency of a conventional channel hotelectron is 1E-8.

[0077] If the probability(estimated to be in the order of 1/100)of thedirection change caused by lattice scattering is considered to beincluded in the value indicated above, it does not provide an advantageto the technology disclosed in the present invention compared to theconventional CHE technology unless the length covering a portion of theelectrical potential difference is within 14Lo[exp(−14Lo/Lo)=1E-6]. Theimpurity concentration with which it is possible to generate anelectrical potential difference corresponding to the electricalpotential barrier V_(B) is more than 2E17 atm/cm³ with the length lessthan that indicated above.

[0078] Meanwhile, the impurity concentration with which it is possibleto generate the electrical potential difference V_(B) within a length of3Lo is 3-4E18 atm/cm3. The length which a carrier is trapped to a chargetrapping means is of the order of 10 nm to the direction of connectingtwo n⁺ regions 121 and 122.

[0079] However, there is a small probability that the direction of acarrier to which energy is supplied is changed by lattice scattering andthat such carrier is injected in the charge trapping means. As describedin detail hereinafter below relating to other embodiments of the presentinvention, this enables higher speed writing if a surface step isdisposed in a carrier moving direction in acarrier-acceleration-injection portion and the carrier which changes nodirection is directly injected in a carrier trapping means of a gateinsulator.

[0080] Next, a method of programming and erasing disclosed in anembodiment of the present invention is now described hereinafter below.Examples relating to a voltage supply at the time of programming are asfollows.

[0081] (1) Supplied to the second n⁺ region 122 is the voltage of morethan V_(B)−2φ_(F2)□V_(B). electrical potential barrier formed betweenthe gate insulator 132 and channel forming semiconductor region 110,φ_(F2): a Fermi-level in a channel forming semiconductor region 110□,e.g. 4.0V.

[0082] This acceleration-electrical potential supply extends a spacecharge region from the second n⁺ region to thecarrier-acceleration-injection portion 112. As a result, energy capableof getting over a potential barrier V_(B) formed at the interface withthe gate insulator 132 is supplied by an electrical potential differencein the space charge region to the carrier which is supplied from thecarrier-supplying portion 111 to the carrier-accelerationinjection-portion and which is moved to the adjacent interface with thesecond n⁺ region 122.

[0083] (2) An electrical potential less than (V_(B)−2φ_(F2)), e.g. 2.2V,is supplied to the first n⁺ region 121.

[0084] (3) An electrical potential which is higher than a gate thresholdvoltage, e.g. 3.3V, is supplied to the gate electrode 140.

[0085] As a result, it is possible to move the carrier to the second n⁺region 122 when a space charge region(carrier path)is formed in asurface of the carrier-supplying portion 111 beneath the gate electrode140 and the carrier is supplied from the first n⁺ region 121 to thecarrier-supplying portion.

[0086] (4) A carrier is not injected into a carrier charge trappingmeans (in gate insulator 132) unless an electrical potential change ismade to the first n⁺ region 121. If the electrical potential less than1.8V is supplied to the first n⁺ region 121, the carrier is suppliedfrom the first n⁺ region 121 to the carrier-supplying portion 111 andfurther moved to the carrier-acceleration-injection portion 112. Out ofcarriers moved to the carrier-acceleration-injection portion 112, acarrier moved to the adjacent interface with the second n⁺ region 122without being affected by lattice scattering is provided with energy andlocally injected in a very narrow region of the carrier charge trappingmeans by getting over the potential barrier.

[0087] In the step as described above, it is possible to store themultivalue information responsive to the supplied electrical potentialif the electrical potential to be supplied to the first n⁺ region 121 iscontrolled in such a manner as to use a variety of voltages such as 0V,0.6V and 1.2V and thus, the carrier supply quantity changes. Theinformation, of course, may be stored in the form of a two-value using0V.

[0088] The order of making an electrical potential in each region toreturn to the standby position(e.g. 0V) is conducted in the order ofgate electrode 140, first n⁺ region 121 and second n⁺ region 122.

[0089] To erase the information(extraction of the trapped carrier), thetrapped carrier is extracted to the gate electrode 140 by making eachvoltage for the first and second n⁺ regions 121 and 122 to be 0V and bysupplying e.g. 9-10V to the gate electrode 140. The extraction of theexcessive quantity of carrier may probably make the gate thresholdvoltage to be that of the depletion mode.

[0090] In the step as described above, there is a possibility that theleakage current is flowed from unselected memory cells to bit lines, ifa memory array to be hereinafter described is comprised of a memory celldisclosed in the present invention. To resolve the problem as describedabove, it is required not to make higher the gate voltage for extractinga carrier or it is necessary to extract the trapped carrier until thedetected threshold voltage reaches the predetermined value by repeatinga step that the gate threshold voltage is detected and the carrier isthen extracted.

[0091] When reading the stored information, e.g. 2.0V which is less thanthe electrical potential (V_(B)−2φ_(F2)) is supplied to the first n⁺region 121, e.g. 0V to the second n⁺ region 122 and e.g. 2.0V to thegate electrode to detect the current which is flowed in the first n⁺region 121. In this step, it is judged to be “0” if, for example, suchcurrent as the leaked current is flowed therein and “1”(in the case oftwo-value storage), if the current more than a microampere unit isflowed therein.

[0092] It is possible to make carrier injection even if the impurityconcentration in the carrier-acceleration-injection portion 112 is thesame as that of the carrier-supplying portion 111 although the carrierinjection efficiency is deteriorated. The carrier-acceleration injectionportion 112 is defined as a space charge region to be formed in thechannel forming semiconductor region 110 by supplying the electricalpotential to the second n⁺ region 122.

[0093] According to a second embodiment of the present invention asshown in FIG. 35, it is possible to inject and trap a carrier charge ina gate insulator 132 on the channel forming semiconductor region at aside of the first n⁺ region 121 if a (first)carrier-acceleration-injection portion 112 a is formed at a side of thefirst n⁺ region 121 and if the electrical potential supplying conditionon the second n⁺ region 122 and first n⁺ region 121 is made reversed. Inthe foregoing case, the carrier-supplying portion 111 is disposed in thechannel forming semiconductor region 110 and sandwiched by the firstcarrier-acceleration injection portion 112 a and the (second)carrier-acceleration injection portion 112. The first and secondcarrier-acceleration injection portions 112 a and 112 are generallycomprised of the same impurity distribution.

[0094] According to an embodiment of the present invention, the highdensity integration is achievable since two storage sites can be made inone gate electrode 140.

[0095] However, when reading the carrier charge information trapped in agate insulator on the first carrier-acceleration injection portion 112a, a space charge layer is made to extend from the second n⁺ region 122to the channel forming semiconductor region 110 (part of the secondcarrier-acceleration injection portion 112)below a part of the gateinsulator trapping the carrier charge supplied from the secondcarrier-acceleration injection portion 112.

[0096] If the condition as indicated above is satisfied, it is possibleto read the information trapped in the gate insulator 132 on the firstcarrier-acceleration injection portion 112 a without being substantiallyaffected by the information trapped in the gate insulator on the secondcarrier-acceleration injection portion 112. For example, if electricalpotential to be supplied to the second n⁺ region 122 is assumed to be1.2V to “read” carrier charge, the impurity concentration in the secondcarrier-acceleration-injection portion 112 is required to be less than2E18 atm/cm³. To read the carrier charge trapped in the gate insulatoron the second carrier-acceleration injection portion 112, a control ofelectrical potential contrary to the foregoing is conducted.

[0097] Meanwhile, in order to form a memory array by integrating theaforesaid memory cell, a gate electrode 140(G) of each memory celladjacent to the direction of a column is connected to a same word lineLw(i); a first n⁺ region 121 (SD1) of each memory cell adjacent to thedirection of a row is connected to a same bit line L_(B)(i)and a secondn⁺ region 12(SD2) of each memory cell adjacent to the direction of acolumn is connected to a same common line L_(c)(i).

[0098] Programming, erasing and reading of information stored in thearrays as described above are possible by changing the cell operationfor a selected cell from(1) a gate electrode 140 to a word lineL_(W)(i), (2) a second n⁺ region 122 to a common line L_(C)(i), and (3)afirst n⁺ region 121 to a bit line L_(B)(i).

[0099] In addition, it is possible to form a second array by connectinga gate electrode 140 to a word line L_(W)(i), a second n⁺ region 122 toa bit line L_(B)(i) and a first n⁺ region 121 to a common line L_(C)(i).Programming and erasing the second array are possible by changing thecell operation for the selected cell from (1) a gate electrode 140 to aword line L_(W)(i), (2) a first n⁺ region 121 to a common line L_(C)(i)and (3)a second n⁺ region 122 to a bit line L_(B)(i).

[0100] When reading the information stored in the array, electricalpotential of the bit line L_(B)(i)is detected by supplying theelectrical potential less than (V_(B)−2φ_(F2)), e.g. 2V to the commonline L_(C)(i) and e.g. 3V to the word line L_(W)(i). If a carrier istrapped in a carrier trapping means (in a gate insulator 132), theoutput electrical potential is so small as to be nearly zero. When theelectron trapped in the carrier trapping means is small in quantity orzero, the output electrical potential becomes nearly 2V which is thesame as that of the common line L_(C)(i).

[0101] According to an embodiment disclosed in the present invention, itis possible to provide a nonvolatile memory cell which is not only of asingle-gate one-transistor cell structure but also enables highefficiency injection and high density integration since local carrierinjection is made from the channel forming semiconductor region 110(carrier-acceleration injection portion) to the gate insulator 132.

[0102] Next, described is a memory cell according to a third embodimentof the present invention in reference to FIG. 4 showing a section of amemory cell and FIG. 5 showing an equivalent circuit thereof.

[0103] The simple structure disclosed in the first and secondembodiments has provided an advantage in terms of manufacturingtechnology. However, it is required to resolve a problem of a leakagecurrent to be caused at the time of reading information which isassociated with the aforesaid excessive erasing as far as the first andsecond embodiments are concerned. Furthermore, it is difficult tooptimize the injection efficiency if the current to supply a carrierfrom the n⁺ region 121 to the channel forming semiconductor region 110at the time of programming is made small.

[0104] According to the third embodiment of the present invention, eachgate electrode(and gate insulator) is independently formed over acarrier-supplying portion 111 and carrier-acceleration-injection portion112 which resulted in not only making the read current to be lessaffected by leakage current from unselected cells due to the excessiveerasing but also improving the injection efficiency at time ofprogramming.

[0105] A well (101) is formed in a surface of a substrate (10) and afirst n⁺ region SD₁ (121) and second n⁺ region SD₂(122) are formed at aninterval in a surface of the well(101).

[0106] A carrier-supplying portion (111) adjacent to the first n⁺ region(121) is formed in a channel forming region between the first n⁺ region(121) and second n⁺ region (122), and a carrier-acceleration injectionportion (112) is formed adjacent to the second n⁺ region (122).

[0107] A first gate electrode G₁ (141) is formed on a first gateinsulator (131) on a surface of the carrier-supplying portion (111). Asecond gate electrode G₂ (142) is formed on a second gate insulator(132) with carrier charge trapping means on a surface of thecarrier-acceleration injection portion (112). The second gate electrode(142) and gate insulation film (132) thereof are extended to cover partand end surface of the n⁺ region (122) side of the first gate electrode(141), and the first gate electrode (141) and second gate electrode(142) are insulated by the second gate insulator (132).

[0108] As described above, an insulator to insulate the first gateelectrode (141) and second gate electrode (142) may be separately formedas another (third) insulation film depending on a method ofmanufacturing thereof without being restricted by the extended gateinsulator.

[0109] The second gate insulator (132) with the carrier charge trappingmeans is of a multilayer structure. Adopted in an embodiment of thepresent invention is a three-layer construction wherein a first layer(132 a) (silicon oxide layer[O]or silicon nitrided ixide layer[ON]); asecond layer (132 b)(silicon nitride film layer[N], tantalum oxidefilm[T] or silicon oxy-nitride film [ON]whose oxygen to nitrogen ratiois smaller than that of the first and a third layer) and a third layer(132 c)(silicon oxide film[O]or silicon nitrided oxide film [ON]) whichforms a potential barrier at the interface with the second gateelectrode (142) are laminated in that order.

[0110] With respect to the second layer of the second gate insulator(132), a carrier trapping level is formed at least at one location atthe interface with the first layer (132 a) or third layer (132 c) orwithin the second layer itself and captured is a carrier injected fromthe carrier-acceleration-injection portion (112) to the second gateinsulator (132).

[0111] Next, described below is a principle of the operation regardingthe memory cell as described above. According to an embodiment of thepresent invention, a carrier is first injected from the first n⁺ region(121) to the carrier-supplying portion (111). Further, the carrier isinjected from the carrier-acceleration injection portion (112) to thesecond gate insulator (132) overcoming the potential barriertherebetween. To inject a carrier from the first n⁺ region (121) to thechannel forming region (110), either of two conditions A and B below isrequired to be satisfied.

[0112] Condition A:

[0113] A potential which is higher than the first gate threshold voltage(V_(th1)) in reference to the first n⁺ region (121) is applied to thefirst gate electrode (141), or a constant predetermined potential isapplied to the first electrode (141) and in a surface of the channelforming region under the first gate electrode (141), a channel isinduced by a potential of the first n⁺ region (121) which is lower thanthe value obtained by having the first gate electrode threshold voltage(V_(th1)) subtracted from the predetermined potential.

[0114] Condition B:

[0115] The first n⁺ region (121) is forward-biased to a channel formingregion and minority carriers are injected in the channel forming region(MC injection).

[0116] Furthermore, two conditions C and D below are required to besatisfied simultaneously in order to inject the carrier injected in thecarrier-acceleration-injection portion (112) via the carrier-supplyingportion (111) into the second gate insulator (132) getting over apotential barrier (V_(B)) between the carrier-acceleration-injectionportion (112) and second gate insulator(132) corresponding to the firstlayer (132 a).

[0117] Condition C:

[0118] Supplied to the second n⁺ region (122) is electrical potentialfor acceleration more than(V_(B)−2φ_(F2)) based on the channel formingsemiconductor region.

[0119] Condition D:

[0120] Supplied to the second gate electrode 142 is electrical potentialfor attracting a carrier more than (V_(B)−φ_(GB)) [φ_(GB): a workfunction difference between a gate material and channel formingsemiconductor region] with reference to the channel formingsemiconductor region 110.

[0121] The electrical potential for attracting a carrier can beestablished independently of the electrical potential in the aforesaidfirst gate electrode and thus, it is possible to achieve high efficientcarrier injection into a carrier storage means by making larger theelectrical potential supplied to the second gate electrode 142 andmaking the electrical potential of the first gate electrode to be assmall as the gate threshold voltage for keeping a channel current to besmall.

[0122] Based on the conditions as described above, a carrier is suppliedfrom the first n⁺ region 121 to the carrier-supplying portion 111.Further, out of carriers moved to the carrier-acceleration injectionportion, supplied to a carrier which is moved to the adjacent interfacewith the second n⁺ region 122 and which is not affected by latticescattering is energy capable of getting over a potential barrier V_(B)by means of interaction between the electrical potential for attractinga carrier supplied to the second gate electrode 142 and the energygenerated by the acceleration-electrical potential supplied to thesecond n⁺ region 122. As a result, the carrier is locally injected frompart(the adjacent interface with the second n⁺ region 122) of thecarrier-acceleration-injection portion 112 into the second gateinsulator 132 getting over the potential barrier V_(B) and locallystored viewed from a plane in the second gate insulator 132, furtherinjection is conducted around the portion in which the carrier isalready trapped.

[0123] Next, a carrier erase (extraction)mechanism in the memory cell isdescribed below. Since the three-layer structure is adopted in thesecond gate insulator (132) according to an embodiment of the presentinvention, two types of erase mechanisms below can be selectively used.

[0124] (a) First Erase Mechanism

[0125] A potential whose polarity is the same as that of the carriercharge is fed to the second gate electrode (142) and the carrier whichis injected and captured in the second gate insulator (132) is returnedvia tunnel to the channel forming region through the first layer (132 a)(The average electric field required for this step is about 8 MV/cm). Toadopt this erase mechanism, a carrier tunnel probability of the firstlayer (132 a) is preferably predetermined to be higher than that of thethird layer (132 c).

[0126] More particularly, the thickness of the first layer (132 a) ismade thinner than that of the third layer (132 c)if the material of eachpotential barrier layer (132 a) and (132 c) is the same. Adopted is suchmaterial combination that the barrier height between the first andsecond layer viewed from the second layer (132 b) to the carrier may belower than that between the second and third layers if each thicknessthereof is the same.

[0127] (b) Second Erase Mechanism

[0128] A potential whose polarity is different from that of the carriercharge is fed to the second gate electrode (142) and the carrier whichis injected and captured in the second gate insulator (132) is extractedby tunnel-transferring the third layer (132 c). To adopt this erasemechanism, a carrier tunnel probability of the third layer (132 c) ispreferably predetermined to be higher than that of the first layer (132a).

[0129] More particularly, the thickness of the third layer (132 c) ismade thinner than that of the first layer (132 a) if the material ofeach potential barrier layer is the same. Adopted is such materialcombination that the barrier height between the second and third layersviewed from the second layer (132 b) to the carrier may be lower thanthat between the first and second layers if each thickness thereof isthe same.

[0130] In order to adopt the first erase mechanism, it is required tosupply to the second gate electrode (142) the potential whose polaritychanges depending on the programming and erasing operation.

[0131] Meanwhile, according to an embodiment of the present invention,both carrier injection and extraction are possible only by supplying tothe second gate electrode (142) the potential with the same polarity anddifferent levels if the second erase mechanism is specifically adopted.

[0132] According to an embodiment of the present invention, the secondgate insulator (132) is of a three-layer structure and the third layer(132 c) as a potential barrier layer is disposed at the interface withthe second gate electrode (142). This makes thinner the second layer(132 b) while keeping the carrier charge trapping function and enablesthe carrier extraction to the gate side by the tunnel transition throughthe third layer (132 c). However, if the potential to extract thecarrier to the gate side is applied to the second gate electrode (142),the electric field caused by this potential is also effective to acarrier within the channel forming region.

[0133] In a conventional memory structure wherein the carrier injectionfrom the channel forming region to the second gate insulator (132) isconducted by a tunnel transition, the probability of a carrier tunnelwithin an insulator (corresponding to the first layer 132 a in anembodiment of the present invention) formed on a surface of a channelforming region is predetermined to be high. This causes the simultaneoustunnel injection from the channel forming region to the second gateinsulator (132) and makes it substantially impossible to extract thecarrier from the second gate insulator (132).

[0134] Meanwhile, it is possible to make adequately low the probabilityof the carrier tunnel across the first layer (132 a) (channel formingregion side) since the carrier injection from the channel forming regionto the second gate insulator (132) is conducted not by tunnel transferbut by overcoming the potential barrier according to an embodiment ofthe present invention. Thus, it is possible to extract a number ofinjected carriers through the third layer (132 c) by reducing the tunnelinjection volume to the second gate insulator to be negligibly smalleven if the second gate electrode (142) is made to be in the highpotential.

[0135] In the case the second erase mechanism is adopted, a siliconoxide film (O) and silicon nitrided oxide film (ON), etc. are preferablyused for the first layer (132 a) and the thickness of each film isdesired to be more than 3 nm. Further, a silicon nitride film (N) andtantalum oxide film (T) are preferably used for the second layer (132 b)and the silicon nitride film thickness is desirably less than 10 nm forthe low voltage programming. However, it is confirmed that theprogramming is possible even with 4 nm thick film.

[0136] The silicon nitride film of the second layer (132 b) may includea smaller volume of oxygen in atomic percent than that in the siliconnitrided oxide film used in the first and third layers. The thickness ofthe tantalum oxide is preferably less than 50 nm. It is recommended thatthe silicon oxide film (O) or the silicon nitrided oxide film (ON) beused for the third layer and the film thickness thereof be more than 2nm.

[0137] That is, combinations among the first, second and third layers ofthe second gate insulator can be designated such as O/N/O, ON/N/O,ON/N/ON, O/N/ON, O/T/O, ON/T/O, ON/T/ON AND O/T/ON.

[0138] It is possible to provide a memory cell which is programmable anderasable with low voltage and same polarity if the memory cell is sostructured that the first layer (132 a) is comprised of a silicon oxidefilm or a silicon nitrided oxide film with the film thickness of 3-4 nmand the third layer, a silicon oxide film or a silicon nitrided oxidefilm with the film thickness of 2-4 nm.

[0139] However, if a silicon oxide film is used for the first layer anda silicon nitrided oxide film is adopted for the third layer, the filmthickness of both layers may be the same. The reason for this is that apotential barrier between the second layer and the first layer viewedfrom the second layer against the silicon nitrided oxide film is low andthe carrier tunnel probability to the third layer becomes larger than apotential barrier between the second layer and the first layer even ifthe film thickness is the same. Also, it is possible to make thethickness of the third layer thinner than that of the first layer if thesilicon nitrided oxide film is used for each layer.

[0140] If the acceleration-electrical potential more than(V_(B)−2φ_(F2)) as specified in condition C is supplied to the second n⁺region 122 and a space charge region is extended from the second n⁺region 122 to the carrier-acceleration-injection portion 112, energygenerated by an electrical potential difference in this extended portionis supplied to a carrier in the carrier-acceleration-injection portion.The shorter the length of the extended portion to which the energy issupplied, the larger quantity of carriers obtain energy to get over thepotential barrier V_(B). Thus, the impurity concentration of thecarrier-acceleration-injection portion is preferably made higher whichis determined to be as high as 2E17-4E18 atm/cm³ according to anembodiment of the present invention.

[0141] If the impurity concentration of thecarrier-acceleration-injection portion (112) is made to be higher thanthat of the carrier-supplying portion (111), a punch-through voltagefrom the second n⁺ region (greater reverse bias is fed to the second n⁺region than to the first n⁺ region.) becomes smaller than that from thefirst n⁺ region if voltage is applied between the first and the secondn⁺ regions (121, 122).

[0142] Next, provided below is the description regarding a nonvolatilememory array so configured that the nonvolatile memory cell as describedabove is aligned in the form of a matrix. FIG. 6 shows an example of aconnection configuration of a first nonvolatile memory array.

[0143] A first n⁺ region SD₁ (121) of each memory cell on a same row isconnected by a bit line (L_(B)). A second n⁺ region SD₂ (122) of memorycells adjacent to the direction of a row is commonly connected andconnected to the direction of a column by a common line (L_(C)) A firstgate electrode G₁ (141) of each memory cell on a same column isconnected by a word line (L_(w)). A second gate electrode G₂ (142) ofeach memory cell on a same column is connected by a control line(L_(S)).

[0144]FIG. 7 shows a connection configuration of a second nonvolatilememory array. A first n⁺ region SD₁ (121) of each cell on a same row isconnected by the bit line (L_(B)). Each second n⁺ region SD₂ (122) ofthe memory cells adjacent to the direction of a row is connected andalso connected by a common line (L_(c)) in the direction of a column. Afirst gate electrode G₁ (141) of each memory cell on a same row isconnected by a word line (L_(w)). A second gate electrode G₂ (142) ofeach memory cell on a same row is connected by a control line (L_(S)).

[0145]FIG. 8 is a signal waveform illustration showing a method ofprogramming and reading a memory array in the first and second circuitconfigurations.

[0146] When programming(writing of information) the selected memorycell, a channel is induced in the surface of a carrier-supplying portion111 depending on the electrical potential of a bit line L_(B) byapplying to a word line L_(W) an electrical potential V_(wpr1) which ishigher than a gate threshold voltage V_(th1) of the first gate electrode141. According to the condition C, the electrical potential which ishigher than the value(V_(B)−2φ_(F2)) is applied to a selected commonline L_(c)(n⁺ region 122) and applied to an unselected common line L_(c)is an adequate electrical potential including zero volt in the directionof the reverse bias which is lower than junction breakdown voltage, e.g.0V. According to the condition D, the electrical potential forattracting a carrier which is higher than (V_(B)−2φ_(GB)) is applied tothe selected control line L_(s)(second gate electrode 142) and appliedto an unselected control line L_(s) is such predetermined electricalpotential, e.g. 0V that the programming may not be caused by tunnelcurrent.

[0147] Applied in advance to a bit line (L_(B)) is a predeterminedpotential (V_(BPr)) which is higher than the value (V_(WPr1)−V_(th1))obtained by subtracting the threshold voltage (V_(th1)) from thepotential (V_(WPr1)) to be fed to the word line (L_(w)). Whenprogramming a memory array, the potential (V_(BPi1)) which is higherthan the difference value (V_(WPr1)−V_(th1)) or the potential (V_(BPi0))which is lower than the difference value (V_(WPr1)−V_(th1)) is appliedthereto depending on the content of the data stored. In this step, it ispossible to program information in the form of a multivalue if theapplied potential (V_(BPr0)) to the bit line (L_(B)) is selected out ofmulti value as shown with broken lines.

[0148] Based on the program operation as described above, a carrierinjected from the first n⁺ region (121) to the carrier-supplying portion(111) is locally injected in the second layer (132 b) by getting overthe potential barrier between the carrier-acceleration-injection portion(112) and second gate insulator 132(first layer 132 a) and thus, theinformation responsive to the potential applied to the bit line (L_(B))is stored in the form of nonvolatility.

[0149] When reading the data stored in the selected memory cell, thereverse bias electrical potential V_(BRD) is applied to the bit lineL_(B) of the memory cell and applied to the control line L_(s) is theelectrical potential V_(CRD) which is higher than the lower value out ofthe programmed gate threshold voltage V_(th2) of the second gateelectrode 142 and also, applied to the word line L_(w) is the electricalpotential V_(WRD) which is higher than the gate threshold voltageV_(th1) of the first gate electrode 141. In the state as describedabove, whether a memory cell is on or off, i.e. the data are stored inthe memory cell is judged by detecting the current(i_(WRD)) flowing inthe bit line (L_(B)) by a sensing amplifier. The data judgment asdescribed above may be made not by directly detecting the current but bythe discharge speed (potential change) of an electric charge which hascharged the bit line.

[0150] However, the methods for configuring and programming a memorycell are not limited to those described above, but may be modified asfollows.

[0151]FIG. 9 is an illustration showing a third modified example of theconnection configuration. A first n⁺ region SD₁ (121) of memory cellsadjacent to the direction of a row is commonly connected and isconnected by a common line (L_(c)) to the direction of a column. Asecond n⁺ region SD₂ (122) of each memory cell in a row direction isconnected by a bit line (L_(B)). A first gate electrode G₁ (141) of eachmemory cell in a column direction is connected by a word line (L_(w)). Asecond gate electrode G₂ (142) of each memory cell in a column directionis connected by a control line (L_(S)).

[0152]FIG. 10 is an illustration showing a fourth modified example of aconnection configuration. A first n⁺ region SD₁ (121) of each memorycells adjacent to the direction of a row is commonly connected andconnected by a common line (L_(c)) to the direction of column. A secondn⁺ region SD₂ (122) of each memory cell in a row direction is connectedby a bit line (L_(B)). A first gate electrode (141) of each memory cellin a column direction is connected by a word line (L_(w)). A second gateelectrode (142) of each memory cell in a column direction is connectedby a control line (L_(s)).

[0153]FIG. 11 shows a section of a nonvolatile memory cell in a fourthembodiment of the present invention. The same symbols as those used inthe previous description represent the same or corresponding portionstherein.

[0154] According to the fourth embodiment of the present invention,contrary to the structure in a third embodiment of the present inventionis the structure that a first gate electrode (141) and gate insulator(131) thereof are superimposed with a second gate electrode and gateinsulator (132) thereof at each end portion wherein the first gateelectrode (141) and gate insulator (131) thereof are extended to cover asurface and end surface at the first n⁺ region (121) side of the secondgate electrode (142).

[0155]FIG. 12 shows a section of a nonvolatile memory cell in a fifthembodiment of the present invention. The same symbols as those used inthe previous description represent the same or corresponding portionstherein.

[0156] According to the fifth embodiment of the present invention, firstand second electrodes (141) and (142) are disposed by having a secondgate insulator (132) formed therebetween and are reciprocally insulatedby the second insulator (132).

[0157] In the first to the fourth embodiments of the present invention,provided previously was the description that the first and secondelectrodes (141) and (142) are insulated with a first insulator (131) ora second (132), but the insulation may be made with other (third)insulator. Or achieved may be multiple insulation in such a manner thatthe first gate insulator (131) or the second (132) is used, or thesecond (132) in combination with other insulation films.

[0158] As shown in FIG. 13 as a sixth embodiment of the presentinvention, in order to reduce the coupling capacitance between the firstgate electrode (141) and second gate electrode (142) and improve a drivespeed, a nitride film (141 b) may be formed in advance on an uppersurface of the gate electrode (141) or an end surface of the gateelectrode (141) can be oxidized to form an oxide film (141 a) or asurface of a side-wall (not shown in accompanying drawings) as aninsulating material may be formed at a side surface of the gateelectrode (141) in place of an oxide film (141 b). It is possible toform the side-wall by uniformly forming an insulating layer on, e.g. amain surface of the substrate (10) and selectively removing theinsulator therefrom via an anisotropic etching method thereof.

[0159]FIG. 14 shows a section of a nonvolatile memory cell in a seventhembodiment of the present invention and FIG. 15, an equivalent circuitto a nonvolatile memory cell in FIG. 14. The same symbols as those usedin the previous description represent the same or corresponding portionstherein. A nonvolatile memory cell in a fourth embodiment of the presentinvention is featured in that the data corresponding to two bits can beindependently stored in a memory cell.

[0160] A well (101) is formed in a surface of the substrate (10) and apair of n regions SD₁ (221) and SD₂ (222) are formed at an interval in asurface of the well (101). In a channel forming region (110) betweeneach n⁺ regions (221) and (222), are formed a carrier-supplying portion(211), and first and second carrier-acceleration-injection portions(212L) and (212R) along the channel direction. Each of thecarrier-acceleration-injection portions (212L) and (212R) is disposedadjacent to each n⁺ regions (221) and (222). The carrier-supplyingportion (211) is disposed between the carrier-acceleration-injectionportions (212L) and (212R).

[0161] A first gate electrode G₁ (241) is formed on a first gateinsulator (131) on a surface of the carrier-supplying portion (211). Afirst one of a second gate electrode G₂₁ (242L) is formed on a first oneof a second gate insulator (132L) with charge storing means on a surfaceof the first carrier-acceleration injection portion (212L). The firstone of the second gate electrode (242L) and gate insulator (132L)thereof are extended to cover part and end surface of the first gateelectrode (241) of the n⁺ region (221) side, and the first gateelectrode (241) and the first one of the second gate electrode (242L)are insulated by the first one of the second gate insulator(132L).

[0162] Likewise, a second one of a second gate electrode G₂₂ (242R) isformed on a second one of a second gate insulator (132R) with chargestoring means on a surface of the second carrier-acceleration-injectionportion (212R). The second one of the second gate electrode (242R) andgate insulator (132R) are extended to cover part and end surface of thefirst gate electrode (241), and the first gate electrode (241) andsecond one of the second gate electrode (242R) are reciprocallyinsulated by the second one of the second gate insulator (132R).

[0163] According to the embodiment of the present invention, each of thesecond gate insulators (132L) and (132R) is of a multilayer structure toachieve a low voltage programming and as described in each embodiment ofthe present invention, a first layer 132 a (silicon oxide layer[O]orsilicon nitrided oxide layer[ON]) forming a potential barrier at theinterface with the channel forming region; a second layer 132 b(siliconnitride film layer[N], tantalum oxide film[T] or silicon oxy-nitridefilm [ON]whose oxygen to nitrogen ratio is smaller than that of thefirst layer and third layer) and a third layer 132 c(silicon oxidefilm[O]or silicon nitrided oxide film [ON]) which forms potentialbarrier at the interface with the second gate electrode (142) arelaminated in their order.

[0164] However, if the low voltage drive as described above is notrequired, each of the second gate insulators (132L) and (132R) isadequate to have charge storing means, e.g. the film may be of atwo-layer structure.

[0165] In the construction as described above, when injecting a carrierinto the first one of the second gate insulator 132L,acceleration-electrical potential is supplied to the first n⁺ region 221and electrical potential for attracting a carrier is supplied to thefirst one of the second gate electrode 242L. Meanwhile, an electricalpotential difference which is larger than the programmed gate thresholdvoltage is supplied between the first one of the second gate electrode242R and the n⁺ region 222 and the electrical potential difference whichis larger than the gate threshold voltage is supplied between the firstgate electrode 241 and the n⁺ region 222.

[0166] Thus, the second carrier-acceleration-injection portion 212Rfunctions as a carrier path to supply a carrier from the n⁺ region 222to the carrier-supplying portion 211 and the carrier is further suppliedto the first carrier-acceleration-injection portion 212L via thecarrier-supplying portion 211. Out of carriers supplied to the firstcarrier-acceleration-injection portion 212L, a carrier moved to theadjacent interface with the n⁺ region 221 without being affected bylattice non-elastic scattering is provided with energy generated byacceleration-electrical potential supplied to the n⁺ region 221 andattracted by the electrical potential for attracting a carrier suppliedto the first one of the second gate electrode 242L, being locallyinjected in a very narrow region of a carrier charge trapping means(agate insulator) getting over the potential barrier.

[0167] When injecting a carrier into the second one of the second gateinsulator, acceleration-electrical potential is supplied to the n⁺region 222 and electrical potential for attracting a carrier is fed tothe second one of the second gate electrode. Meanwhile, the electricalpotential difference which is larger than the programmed gate electrodethreshold voltage is supplied between the first one of the second gateelectrode and the n⁺ region 221 and an electrical potential differencewhich is larger than the gate threshold voltage is supplied between thefirst gate electrode 241 and n⁺ region 221.

[0168] Thus, the first carrier-acceleration-injection portion 212Rfunctions as a carrier path to supply a carrier from the n⁺ region 221to the carrier-supplying portion 211 and the carrier is further suppliedto the second carrier-acceleration-injection portion 212R via thecarrier-supplying portion 211. Out of carriers supplied to the secondcarrier-acceleration-injection portion 212R, a carrier transported tothe adjacent interface with the n⁺ region 222 without being affected bynon-elastic lattice scattering is provided with energy generated by theacceleration-electrical potential supplied to n⁺ region 222 andattracted by the electrical potential for attracting a carrier suppliedto the second one of the second gate electrode 242R, being locallyinjected in a very narrow region of the carrier charge trapping meansgetting over the potential barrier.

[0169] According to the above embodiment of the present invention, it ispossible to independently memorize the data stored in each of the secondgate insulators (132L) and (132R) and thus, to store two-bit data in onecell which results in providing a high integration density memory.

[0170] However, it is possible to program a memory cell with low voltageif each of the second gate insulators (132L) and (132R) is of athree-layer structure and a carrier injection from a channel formingregion to a gate insulator is performed by getting over the potentialbarrier, according to the fourth embodiment of the present invention.

[0171] Furthermore, if the carrier is extracted to a gate electrode bycontrolling each carrier tunnel probability of a first layer and a thirdlayer of the second gate insulators (132L) and (132R) in the same manneras described above, both carrier injection and extraction are achievableby feeding to the gate electrode the potential whose polarity is thesame and whose level is different.

[0172]FIG. 16 shows a section of a nonvolatile memory cell in a eighthembodiment of the present invention. The same symbols as those used inthe previous description represent the same or corresponding portionstherein.

[0173] The structure of a memory cell disclosed in the seventh and theeighth embodiment of the present invention is different with respect toa relation between the upper and lower portions of an electrode whereinboth ends of the first gate electrode 241(and a gate insulator or otherinsulator 131 c) are formed to cover the end portion and end surface ofeach of the first one and second one of the second gate electrodes(242L) and (242R).

[0174] The same advantage as that in the seventh embodiment of thepresent invention is achieved in this eighth embodiment thereof.Furthermore, provided is a structure suitable for interconnecting thefirst gate electrode (241) across the n⁺ regions (221) and (222)according to the eighth embodiment.

[0175]FIG. 17 shows a section of a nonvolatile memory cell in a ninthembodiment of the present invention. The same symbols as those used inthe previous description represent the same or corresponding portionstherein.

[0176] According to the ninth embodiment, a first gate electrode (241)is formed on the first gate insulator (131) on a surface of thecarrier-supplying portion (211). Each of the second gate insulators(132L) and (132R) is formed between each of the carrier-accelerationinjection portions (212L) and (212R) and each of the second gateelectrodes (242L) and (242R), and further, extended to a gap between thefirst gate electrode (241) and each of the second gate electrodes (242L)and (242R).

[0177] Each one of the second gate electrodes (242L) and (242R) isformed as a pair of side-walls on the second gate insulator (132) on asurface of each of the carrier-acceleration injection portions (21L) and(212R). A word line (L_(w)) is connected to an upper portion of thefirst gate electrode (241). The same advantage as that in the seventhand eighth embodiments of the present invention is achieved in thisninth embodiment.

[0178] In the ninth embodiment of the present invention, however, theword line (L_(w)) is connected to the first gate electrode (241) afterforming a second gate insulator (132) on the entire upper surface of thefirst gate electrode (241) and by having an upper surface thereofexposed. As shown in FIG. 18, the insulator (132) becomes thin inthickness at an upper portion of the gate electrode (241) and theinsulation effect on the upper portion is deteriorated. In the case ofthe foregoing, an end surface of the gate electrode (241) can beoxidized to form an oxide film (241 a) or in place of the oxide film(241 a), a side-wall insulator (not shown in accompanying drawings) asinsulating material may be formed on a side surface of the gateelectrode (241) as a tenth embodiment shown in FIG. 18.

[0179] As described above, the high speed and low voltage programming isachievable since it is possible to reduce the capacitance between eachgate if each gate electrode is insulated together with not only gateinsulators but also other insulators.

[0180]FIG. 19 shows a section of a nonvolatile memory cell in a eleventhembodiment of the present invention. The same symbols as those used inthe previous description represent the same or corresponding portionstherein.

[0181] According to the eleventh embodiment of the present invention,each of the second gate insulators (132L) and (132R) is of a three-layerstructure as described above, while the first and second gate electrodesare insulated from each other by the insulator (401) formed on a surfaceof each of the second gate electrodes (242L) and (242R) and a side-wallinsulator (402) formed on a side surface of each of the second gateelectrodes (242L) and (242R). Further, part of the second gate insulator(132) is etched to reform the first gate insulator (103). The sameadvantage as that in the embodiments of the present invention isachievable in this eleventh embodiment.

[0182]FIG. 20 is an illustration showing a section of a twelfthembodiment of the present invention. The same symbols as those used inthe previous description represent the same or corresponding portionstherein. This embodiment is featured in that steps SL and SR aredisposed on a surface of said each carrier-acceleration-injectionportion 212L and 212R.

[0183] The steps SL and SR are applicable to any of embodiments of thepresent invention, but provided below is the description referring to atenth embodiment of the present invention used for describing theillustration 18.

[0184] The first and second n⁺ regions 221 and 222 have their respectiven-type n regions 221 n and 222 n which are shallow and relatively low ina concentration(1E19-1E20 atm/cm³). The impurity concentration of the nregions 221 n and 222 n is lower than that (1E21-1E20 atm/cm³) of the n⁺regions 221 and 222 and the n regions 221 n and 222 n are disposed tonot only improve the breakdown voltage between thecarrier-acceleration-injection portions 212L and 212R and but alsoinduce a carrier path in the vicinity of a surface of a semiconductor byshallowing the depth of the n regions. The structure as described aboveis applicable to each of the embodiments of the present invention.

[0185] The n regions 221 n and 222 n are disposed on a portion notbeyond a top of each of steps SL and SR, that is, so that a part of eachof the n regions may not be located at the top thereof. A top of each ofsteps SL and SR is disposed within the distance of a space charge regionextended from n regions 221 n and 222 n to thecarrier-acceleration-injection portions 212L and 212R. A step differenceof each of the steps SL and SR is preferably within 110 nm and the stepdifference may be of a slope or a perpendicularity as shown in theillustration.

[0186] Next, described below is a function of the step SR (SL) referringto FIG. 21. Carriers supplied from the carrier-supplying portion 211 toan adjacent surface of the carrier-acceleration-injection portion(awhite arrow A) 212R and accelerated in the portion have large energy inthe transport direction. Since the step SR has a vertical component inthe transport direction, part of the carriers (a black arrow B) isdirectly injected from the step SR into the second one of the secondgate insulator 132R without being affected by lattice scattering andtrapped in a carrier charge trapping means. This permits the carrierinjection quantity to be more than one order of magnitude largercompared to the case where there is no step SR on a surface of thecarrier-acceleration-injection portion 212R.

[0187] Furthermore, the step structure as described above makes acarrier path move near to a surface of the step in thecarrier-acceleration-injection portion. Thus, the co-operative effect ofthe acceleration potential supplied to the n⁺ region 222 and theattracting electrical potential supplied to the second one of the secondgate electrode 242R is effectively applied to the carriers not injectedand left in the carrier-acceleration-injection portion 212R and makes itpossible to prevent the energy of the carriers from being attenuatedwhich results in making efficient local injection(a black arrow C) ofthe carriers into the second one of the second gate insulator at theadjacent interface with n⁺ region(n region 222 n).

[0188] Contrary to the foregoing, as shown in FIG. 22, if a surface ofthe carrier-acceleration-injection portion 212R is flat and theelectrical potential for attracting a carrier is small, the carrier ismoved from the surface of the carrier-acceleration-injection portion212R to the inside thereof as the carrier approaches from a pinch-offpoint to the n⁺ region 222. Even if the carrier to which energy issupplied in the carrier-acceleration-injection portion is scattered andinjected into the gate insulator 132R, the carrier injection quantitybecomes smaller by one order of magnitude if the distance which isrequired for the carrier to reach a surface of thecarrier-acceleration-injection portion is, for example, longer than 2.3times the mean free path.

[0189] According to the aforesaid embodiment of the present invention,it is possible for a carrier to move in a surface of thecarrier-acceleration-injection portion 212R even if the electricalpotential for attracting the carrier is small. This enables highefficiency local injection.

[0190] A well structure shown in FIG. 20 is called a triple well whichis a two-layer structure comprising n-well 102 and p-well 101. Thistriple well structure enables applying either positive or negative biasto the p-well with respect to a semiconductor substrate. Also, thetriple well structure as described above is applicable to each of theaforesaid embodiments of the present invention.

[0191] Next, provided is the description of a nonvolatile memory arrayso configured and structured that a nonvolatile memory cell is alignedin the form of a matrix. FIG. 23 shows an example of a firstconfiguration for the nonvolatile memory array and FIG. 24, an exampleof a second configuration for the nonvolatile memory array.

[0192] In FIG. 23, each of n⁺ SD₁ (221) and SD₂ (222) of memory cellsadjacent to a direction of a row is commonly connected and in thedirection of a column is connected by a bit line (L_(B)). A first gateelectrode G₁ (241) in a column is connected by a word fine (L_(w)). Afirst one of a second gate electrode G₂₁ (242L) in a column is connectedby a first control line (L_(SL)) and a second one of a second gateelectrode G₂₂ 242R) in a column is connected by a second control line(L_(SR)).

[0193] In FIG. 24, a first n⁺ region SD₁ (221) in each nonvolatilememory cell in a same row is connected by a bit line (L_(B)). A secondn⁺ region SD₂ (222) of memory cells adjacent to the direction of a rowin a column is connected by a common line (L_(c)). A first gateelectrode G₁ (241) in a column is connected by a word line (L_(w)). Afirst one of a second gate electrode G₂₁ (242L) in a column is connectedby a first control line (L_(SL)) and a second one of a second gateelectrode G₂₂ (242R) in a column is connected by a second control line(L_(SR)).

[0194]FIG. 25 shows electrical potential supplying conditions applicablewhen programming, a cell between a bit line L_(B)(i) and bit lineL_(B)(i+1)out of memory cells constituting an array in FIG. 23.

[0195] (1) Carrier injection into the second one of the second gateinsulator 132R:

[0196] An electrical potential of the bit line L_(B)(i) is predeterminedto be an electrical potential V_(bitp) which is higher than the valueobtained by subtracting the threshold voltage V_(th1) of the first gateelectrode 241 from the electrical potential V_(Ws1) of a selected wordline L_(w)(i).

[0197] Next, an electrical potential V_(Ws1) which is higher (at theabsolute value) than the threshold voltage V_(th1) of the first gateelectrode 241 is supplied to a selected word line L_(W)(i); anacceleration-electrical potential V_(bits1) which is higher than(V_(B)−2φ_(F3)), to the bit line L_(B)(i+1); the electrical potentialfor attracting a carrier V_(crls1) which is higher than thevalue(V_(B)−φ_(GB)),to a control line L_(SR)(i); the electricalpotential V_(crlns1) which is higher than the gate threshold voltageV_(th2-1) of the first one of the second gate electrode 241L, to thecontrol line L_(SL)(i); and an electrical potential V_(wns1) which islower than the gate threshold voltage of said first gate electrode 241,to an unselected word line L_(W)(i)(A reference point covering theelectrical potentials as described so far is a channel formingsemiconductor region.)

[0198] After the electrical potential V_(Ws1) is supplied to the wordline L_(W) (i), the electrical potential of the bit line L_(B) (i) ischanged and programming information is selected by a difference value[V_(bit1) higher than (V_(WSl)−V_(th1)) or V_(bit0) lower than(V_(WSl)−V_(th1))].

[0199] According to the electrical potential supplying method asdescribed above, the same electrical potential is determined to besupplied to a bit line L_(B) (i) starting from a bit line L_(B)(i+1)every other line and more particularly, determined to be V_(bit1)or V_(bit0) from the bit line L_(B)(i) every other line in response tothe programming information. A description was made to the two-valuewith respect to the selected electrical potential for the information,but it is possible to program multivalue information, if V_(bit0) isused as multilevel(V_(bit0-1), V_(bit0-2) and V_(bit0-3)).

[0200] (2) Carrier injection in the first one of the second gateinsulator 132L:

[0201] An electrical potential of a bit line L_(B)(i+1) is predeterminedto be the electrical potential V_(bitp) which is higher than the valueobtained by subtracting the threshold voltage V_(th1) of the first gateelectrode 241 from the electrical potential V_(WSl) of a selected wordline L_(W) (i).

[0202] Next, an electrical potential V_(Ws1) which is higher(at theabsolute value) than the threshold voltage(V_(th1))of the first gateelectrode 241 is supplied to the selected word line L_(W); theacceleration-electrical potential V_(bits1) which is higher than(V_(B)−2φ_(F3)), to a bit line L_(B)(i); the electrical potential forattracting a carrier V_(crls1) which is higher than thevalue(V_(B)−φ_(GB)), to a control line L_(SL)(i); the electricalpotential V_(crlnsl) which is higher the gate threshold voltageV_(th2-2) of the second one of the second gate electrode 242R to acontrol line L_(SR)(i); and the electrical potential V_(wns1) which islower than the gate threshold voltage of said first gate electrode 241,to an unselected word line L_(W)(i)(A reference point covering theelectrical potentials as described so far is a channel formingsemiconductor region.)

[0203] After the electrical potential V_(Ws1) is supplied to the wordline L_(W), the electrical potential of said bit line L_(B) (i+1) ischanged and programming information is selected by the difference value[V_(bit1) higher than (V_(WSl)−V_(th1)) or lower than V_(bit0)].

[0204] According to the electrical potential supplying method asdescribed above, the same electrical potential is determined to besupplied to a bit line L_(B)(i) starting from a bit line L_(B)(i+1)everyother line and more particularly, determined to be V_(bit1) or V_(bit0)from the bit line L_(B)(i+1)every other line in response to theprogramming information. A description was made to the two-value withrespect to the selected electrical potential for the information, but itis possible to program multivalue information, if V_(bit0) is used asmultilevel(V_(bit0-1), V_(bit0-2) and V_(bit0-1)).

[0205] As described above, programming according to an embodiment of thepresent invention is to be carried out as per one cell. With respect tothe carrier injection in the adjacent two cells, while injecting acarrier in the second one of the second gate insulator 132R in one cell,it is possible to inject the carrier in the first one of the second gateinsulator 132L in the other cell. However, if the programminginformation is different, it is required for the adjacent cells to carryout the programming two times. In the step as described above, if thestandby electrical potential is supplied to the control lineL_(SL)(L_(SR)), the cell concerned is not programmed.

[0206] Next, referring to FIG. 26, described below are electricalpotential supplying conditions applicable when reading the informationstored in each memory cell of the array.

[0207] (1) Reading of the information stored in the first one of thesecond gate insulator 132L:

[0208] An electrical potential V_(wr) which is higher than the firstgate threshold voltage V_(th1) is supplied to a selected word line L_(W)(i)and the electrical potential V_(bitrr) in a reverse direction to thechannel forming semiconductor region 110, to a bit line L_(B)(i+1). Theelectrical potential V_(bitrr) is the one which is lower than the value(V_(B)−2φ_(F2)).

[0209] Furthermore, the electrical potential V_(bitF1) which is lower(including zero) than the electrical potential V_(bitrr) is supplied toa bit line L_(B) (i); the electrical potential V_(crlrc) which is higher(at the absolute value) than the maximum value V_(th2-2max) of thesecond one of the second gate threshold voltage, to the control lineL_(SR) (i); and the electrical potential between a plurality of theprogrammed first one of the second gate threshold voltage V_(th2-1-i)and V_(th2-1-(i+1)), to a control line L_(SL)(i). It is judged from theaforesaid step that if a current is flowed to the L_(B)(i+1), the firstone of the second gate threshold voltage is less than the valueV_(th2-1-i) and if not, the voltage is more than value V_(th2-1-(i+1)).

[0210] (2) Reading of the information stored in the second one of thesecond gate insulator 132R:

[0211] An electrical potential V_(wr) which is higher than the firstgate threshold voltage V_(th1) is supplied to a selected word line L_(W)(i) and the electrical potential V_(bit1r) in a reverse direction to thechannel forming semiconductor region 110, to a bit line L_(B)(i+1). Theelectrical potential V_(bit1r) is the one which is lower than the value(V_(B)−2φ_(F2)).

[0212] Furthermore, the electrical potential V_(bitrl) which is lower(including zero) than the electrical potential V_(bit1r) is supplied toa bit line L_(B)(i+1); the electrical potential V_(Crllc) which ishigher (at the absolute value) than the maximum value V_(th2-1max) ofthe first one of the second gate threshold voltage, to a control lineL_(SR)(i); and the electrical potential between a plurality of theprogrammed second one of the second gate threshold voltage V_(th2-2-i)and V_(th2-2-(i+1)), to a control line L_(SR)(i). It is judged from theaforesaid step that if a current is flowed to the L_(B)(i), the secondone of the second gate threshold voltage is less than the valueV_(th2-2-i) and if not, the voltage is more than the valueV_(th2-2-(i+1)).

[0213] Current detection may be conducted by detecting the currentitself or detecting electrical potential change in the bit line L_(B)charged to the specified electrical potential within a predeterminedtime. Also, the V_(th) level less than V_(th2-1-i) and V_(th2-2-i) canbe judged depending on the value of a current to be detected.

[0214] Next, described is a manufacturing method referring to FIGS.27-34 showing sections of a memory array manufactured in an arrayconfiguration of the memory cell disclosed in a twelfth embodiment ofthe present invention with respect to FIG. 20.

[0215] As shown in FIG. 27, n-well 102 and p-well 101 are formed in asurface of p type semiconductor substrate 10 and a surface of the p-well101 is oxidized to form a thermal oxide film with thickness of 5 nm. Asurface layer 201 is then formed by introducing by ion implantation in asurface of the p-well impurity(boron according to the twelfth embodimentof the present invention)to be an impurity for the carrier-supplyingportion in a subsequent step.

[0216] Next, the thermal oxide film is removed by wet etching and athermal oxide film 130 with thickness of 7 nm is again formed on asurface of the p-well 101 by pyrogenic oxidization at 800° C. Aphosphorous-doped polysilicon thin film 300 with thickness of 200 nm isfurther formed and a silicon nitride film 301 with thickness of 100 nmis then formed. In addition, a photoresist is coated on a surface of asubstrate and is patterned to a shape of the first gate electrode 241,resulting a photoresist mask 401.

[0217] Next, the silicon nitride film 301 and polysilicon thin film 300are etched using the photoresist 401 as a mask as shown in FIG. 28. Apolysilicon film 300 is thus fabricated to the shape of the firstelectrode 241.

[0218] After the patterned polysilicon film is cleaned, a thermal oxidefilm 241 a with thickness of 30 nm is grown on sidewalls of the firstgate electrode (polysilicon) 241 by pyrogenic oxidization at 800° C. Asilicon nitride film 302 is formed evenly over the surfaces to be 10 nmthick and further, a polysilicon layer 303 is formed uniformly to be 80nm in film thickness.

[0219] Next, as shown in FIG. 29, a horizontal portion of thepolysilicon 303 is etched by a so-called reactive ion etching (RIE) anda sidewall 303SW is left close to a side surface of the first gateelectrode 241. Further, the silicon nitride film 302 is etched using thepolysilicon sidewall 303SW as a mask. In the process as described above,the silicon nitride film 301 on a surface of the first gate electrode isleft thereon since the silicon nitride film 301 is thicker than thesilicon nitride film 302.

[0220] Then, as shown in FIG. 30, the polysilicon side wall 303SW closeto a side surface of the first gate electrode 241 is removed by anisotropic etching method and the silicon oxide film 130 is etched usingas a mask the silicon nitride film 302 left beneath the now removedpolysilicon sidewall and side surface of the polysilicon.

[0221] Next, a surface of the p-well is etched to the depth of 50 nmusing as masks the silicon nitride film 302 and the silicon oxide filmleft as a result of the process as described above. Side surfaces of anetched trench 101T become steps SL and SR to be formed in each surfaceof carrier-acceleration-injection portions 212L and 212R in thesubsequent process. A bottom surface of the etched trench 101T becomesn⁺ regions 221 and 222 in its greater parts.

[0222] However, when etching a trench 101T using an isotropical etchingtechnology, side etching is also carried out (Provided hereinafter belowis a description of utilizing this side etching with reference to FIG.31.). After a 5 nm thick thermal oxide film is grown, arsenic formingthe regions 221 n and 222 n is injected by low energy(less than 10 KeV)ion implantation in advance using as masks the silicon oxide film 130and silicon nitride film 302. This ensures self-alignment of the stepsSL and SR with n⁺ regions 221 and 222 since the positioning is carriedout using the same mask. In the process as described above, the arsenicimplantation for the n regions 221 n and 222 n is not required whichwill be described hereinafter below relating to FIG. 32.

[0223] Next, as shown in FIG. 31, a thermal oxide film (not shown in afigure) with thickness of 5 nm is formed in the etched trench 101T andthen, the silicon nitride film 302, thermal oxide film 130 and thethermal oxide film in the etched trench are etched in their order and awell surface between the first electrodes is exposed.

[0224] Furthermore, a silicon oxide film 132 a to be a first layer foreach of the second gate insulators 132L and 132R is formed to be 3.5-4nm thick by a pyrogenic oxidization method at 800° C. Then, a siliconnitride film 132 b to be a second layer is formed to be 4 nm thick by aCVD method and a silicon oxide film 132 c to be a third layer is formedto be 3-3.5 nm thick by a CVD method. Thereafter, the silicon oxide film132 b is oxidized by a pyrogenic oxidization method at 800° C. Theprocess as described above completes formation of a second gateinsulator 132 which is of a three-layer structure incorporating acarrier charge trapping means. A first gate insulator 131 is alreadyformed with self-alignment to the first gate electrode 241.

[0225] Next, as shown in FIG. 32, a polysilicon film (not shown in thefigure) as a protective film for the second gate insulator 132 is formeduniformly to be 10 nm film thick. Implanted through gate insulators byan ion implantation method is a first conductivity type impurity (boronaccording to the embodiment of the present invention) to be impurity inthe carrier-acceleration-injection portions 212L and 212R in asubsequent process. The impurity in the carrier-acceleration-injectionportions 212L and 212R is implanted to form thecarrier-acceleration-injection portion self-aligned to the first gateelectrode 241 by using itself as a mask.

[0226] The phenomenon as described above results in that when forming afirst one of a second gate electrode 242L and second one of the secondgate electrode 242R adjacent to a side wall of a first gate electrode241 which is described hereinafter below relating to FIG. 32, theimpurity 202 in the carrier-acceleration-injection portion isself-aligned to the first one of the second gate electrode 242L andsecond one of the second gate electrode 242R.

[0227] Next, as shown in FIG. 32, a phosphorous doped polysilicon isformed evenly to be 100 nm thick (not shown in a figure) and ahorizontal portion thereof is etched by an anisotropical RIE method,polysilicon side walls 242L and 242R being left adjacent to a sidesurface of the first gate electrode 241. The phosphorous doped side wallbecomes the first one of the second gate electrode 242L and second oneof the second gate electrode 242R. In the process as described above, aprotective polysilicon is also etched as referred to in FIG. 31.Further, an oxide film 242 a with film thickness of 7 nm is formed on asilicon side wall surface via a pyrogenic oxidization method at 800° C.

[0228] Next, implanted by an ion implantation method in a surface of theetched trench is n region impurity (arsenic according to the twelfthembodiment of the present invention) using as masks polysiliconsidewalls 242L and 242R to form n regions 221 n and 222 n. This enablesautomatic adjustment of each position of an end portion of the n regionand steps SL and SR of carrier-acceleration-injection portion. Then, asilicon nitride film (not shown in the figure) is formed evenly to havea 30 nm film thickness by a CVD method and a horizontal portion thereofis etched by an anisotropic RIE method, a sidewall 242 b of a siliconnitride film being left at each side of polysilicons 242L and 242R.

[0229] Furthermore, implanted in a surface of the etched trench by anion implantation method using the silicon nitride film as a mask isimpurity (arsenic according to the twelfth embodiment of the presentinvention) to form the n⁺ regions 222 and 221 whose dose is larger byone to two orders of magnitude than the impurity. Thereafter, theion-implanted impurity is heat-treated and activated.

[0230] Next, as shown in FIG. 33, the oxide film on the polysiliconsidewall is etched and the three-layer film 132 left between siliconnitride films 242 b is etched away. Further, after titanium or cobalt isevaporated on an entire surface, the evaporated titanium or cobalt filmis heat-treated. The portions which are exposed to the outside byetching, i.e. an upper surface of the polysilicon side wall and highconcentration portions of n⁺ regions 222/221 s, are silicided. Any metalwhich has not yet been reacted is etched to be removed.

[0231] The low resistance n⁺ regions 222/221 and the first one andsecond one of the second gate electrode 242L, 242R are formed throughthe process as described above and low resistance bit lines, commonlines and control lines can be formed by continuously forming n⁺ regionsand electrodes in other cells.

[0232] Next, as shown in FIG. 34, a silicon oxide film 251 is formed bya CVD method to make film thicker than that of the first gate electrode241 and left only between the first gate electrodes. Further, thesilicon nitride film 301 on an exposed upper surface of the first gateelectrode is selectively etched (to the silicon oxide film) and thefirst gate electrode is exposed to form by a CVD method phosphorousdoped polysilicon 252 to be 100 nm thick. In addition, tungsten silicide252 s is formed by a CVD method on the phosphorous doped polysilicon 252to be 50 nm thick and the first gate electrodes 241 of a plurality ofcells are connected each other. A two-layer film comprising saidtungsten silicide 252S and polysilicon 252 is fabricated fitted to aplane shape of the word line L_(W) based on the well known lithographytechnology.

[0233] Furthermore, a bit line, a common line, a word line and controlline are connected to peripheral circuits using multilayerinterconnection technology. To connect a control line to a peripheralcircuit, it is required to form a connection-pad shaped photoresist at astage prior to the anisotropic polysilicon etching.

[0234] Provided below are advantages according to the present invention.

[0235] (1) When injecting a carrier in a gate insulator with a carriercharge trapping means from a channel forming semiconductor region, localcarrier injection is possible getting over a potential barrier from aportion(the adjacent interface with the second n⁺ region 122 out ofcarrier-acceleration-injection portions) of the channel formingsemiconductor region. This results in not only enabling high efficiencyinjection and low voltage and high speed programming, but also providinga high integration density memory cell.

[0236] (2) Two gate electrodes are independently formed over a channelforming semiconductor region and an electrical potential for attractinga carrier is supplied to a gate electrode formed in a region in whichthe carrier is locally injected. This enables high efficiency injectionin the gate insulator owing to the interaction between theacceleration-electrical potential to be supplied to the n⁺ region 122and the electrical potential for attracting a carrier even if the numberof the carriers to be supplied from the first n⁺ region 121 to a channelforming semiconductor region is reduced.

[0237] (3) Second gate electrodes and insulators thereof are disposed onboth sides of a first gate electrode and carrier supply and attractionare independently conducted. Furthermore, the carrier within the channelforming region can be independently injected in each of the secondinsulators. This results in not only enabling a memory cell to storetwo-bit data therein but also reducing programming current as well as inproviding a high integration density memory.

[0238] (4) The carrier injection and extraction thereof to and from thesecond gate insulator can be conducted only by applying to the secondgate electrode an electrical potential whose polarity is the same bothfor the injection and extraction. This simplifies circuit configurationfor the carrier injection and extraction.

[0239] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetailes may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A nonvolatile memory cell wherein first andsecond impurity regions of opposite conductivity type are formed in amain surface of a substrate and separated therebetween by a channelforming semiconductor region of one conductivity type in said mainsurface of said substrate and a gate electrode is formed on a gateinsulator on said channel forming semiconductor region, carriers beinginjected and stored in a carrier trapping means of said gate insulatorfurther comprising: providing an acceleration-electrical potentialsupplying means to selectively supply the acceleration-electricalpotential to one out of said first and second impurity regions at oneside; said channel forming semiconductor region includes acarrier-supplying portion and a carrier-acceleration-injection portiondisposed along a carrier transport direction; said carrier-supplyingportion supplies to said carrier-acceleration-injection portion carrierssupplied by the other one out of said first and second impurity regionsat the other side; and said carrier-acceleration-injection portion makeslocal injection of carriers supplied from said carrier-supplying portioninto said gate insulator in the vicinity of adjacent said one out ofsaid first and second impurity regions at one side to which saidaccelerated electrical potential is supplied.
 2. The nonvolatile memorycell according to claim 1 further comprising: said carrier-supplyingportion is disposed adjacent to said first impurity region and saidcarrier-acceleration-injection portion is disposed adjacent to saidsecond impurity region; said gate electrode is formed to integrallycover said carrier-supplying portion and saidcarrier-acceleration-injection portion; said acceleration-electricalpotential supplying means supplies said acceleration-electricalpotential to said second impurity region; said carrier-supplying portionsupplies said carriers supplied from said first impurity region to saidcarrier-acceleration-injection portion; and saidcarrier-acceleration-injection portion makes local injection of carriersfrom said carrier-supplying portion into said gate insulator adjacent tosaid second impurity region.
 3. The nonvolatile memory cell according toclaim 1 further comprising: a first carrier-acceleration-injectionportion is disposed adjacent to said first impurity region and a secondcarrier-acceleration-injection portion is disposed adjacent to saidsecond impurity region, said carrier-supplying portion being disposedbetween said first and second carrier-acceleration-injection portions;said gate electrode is formed to integrally cover said carrier-supplyingportion and said first and second carrier-acceleration-injectionportions; and said acceleration-electrical potential supplying meanssupplies acceleration-electrical potential to said second impurityregion when injecting carriers from said secondcarrier-acceleration-injection portion into said gate insulator, and tosaid first impurity region when injecting into said gate insulatorcarriers from said first carrier-acceleration-injection portion.
 4. Thenonvolatile memory cell according to claim 1 further comprising: saidcarrier-supplying portion is disposed adjacent to said first impurityregion and said carrier-acceleration-injection portion is disposedadjacent to said second impurity region; said gate insulator iscomprised of a first gate insulator disposed on said carrier-supplyingportion and a second gate insulator on saidcarrier-acceleration-injection portion; said gate electrode is comprisedof a first gate electrode and second gate electrode which are insulatedfrom each other wherein said first gate electrode is disposed above saidcarrier-supplying portion through said first gate insulator and whereinsaid second gate electrode is disposed above saidcarrier-acceleration-injection portion through said second gateinsulator; said acceleration-electrical potential supplying meanssupplies acceleration-potential to said second impurity region; saidcarrier-supplying portion supplies carriers from said first impurityregion to said carrier-acceleration-injection portion; and saidcarrier-acceleration-injection portion makes local injection of carrierssupplied from said carrier-supplying portion into said second gateinsulator adjacent to said second impurity region.
 5. The nonvolatilememory cell according to claim 4 further comprising a means forsupplying electrical potential for attracting a carrier which suppliesto said second gate electrode an electrical potential for attractingsaid carrier toward said second gate insulator under said second gateelectrode.
 6. The nonvolatile memory cell according to claim 4 whereinan insulating material is formed at least on end surfaces of one gateelectrode out of said first and second gate electrodes.
 7. Thenonvolatile memory cell according to claim 6 wherein said insulatingmaterial formed on said end surfaces of said one gate electrode is of asidewall insulating material left alter anisotropically etching aninsulating material formed uniformly on said main surface of saidsubstrate.
 8. The nonvolatile memory cell according to claim 6 whereinsaid insulating material formed on said end surfaces of said one gateelectrode is of an oxide film formed by oxidizing said one gateelectrode.
 9. The nonvolatile memory cell according to claim 4 whereinan insulator is formed to insulate said first gate electrode from saidsecond gate electrode.
 10. The nonvolatile memory cell according toclaim 4 wherein said second gate electrode and said second gateinsulator thereof are extended to cover a top surface and an end surfaceat said second impurity region side of said first gate electrode. 11.The nonvolatile memory cell according to claim 4 wherein said first gateelectrode and said first gate insulator thereof are extended to cover atop surface and an end surface at said first impurity region side ofsaid second gate electrode.
 12. The nonvolatile memory cell according toclaim 1 wherein: said carrier-acceleration-injection portion comprises afirst carrier-acceleration-injection portion formed adjacent to saidfirst impurity region and a second carrier-acceleration-injectionportion adjacent to said second impurity region wherein saidcarrier-supplying portion is disposed between said firstcarrier-acceleration-injection portion and said secondcarrier-acceleration-injection portion; said gate insulator is comprisedof a first gate insulator disposed on said carrier-supplying portion andtwo second gate insulators, wherein a first one of said second gateinsulators is formed on said first carrier-acceleration-injectionportion and said second one of said second gate insulators is formed onsaid second carrier-acceleration-injection portion; said gate electrodeis comprised of a first gate electrode and two second gate electrodeswherein a first one of said second gate electrodes and a second one ofsaid second gate electrodes are insulated from each other, wherein saidfirst gate electrode is disposed above said carrier-supplying portionthrough said first gate insulator and said first one of said second gateelectrodes is disposed above said first carrier-acceleration-injectionportion through said first one of said second gate insulators, andwherein said second one of said second gate electrodes is disposed abovesaid second carrier-acceleration-injection portion through said secondone of said second gate insulators; and said acceleration-electricalpotential supplying means supplies acceleration-electrical potential tosaid second impurity region when injecting carriers from said secondcarrier-acceleration-injection portion into said second one of saidsecond gate insulators, and to said first impurity region when injectingcarrier from said first carrier-acceleration-injection portion into saidfirst one of said second gate insulators.
 13. The nonvolatile memorycell according to claim 12 further comprising a means for supplyingelectrical potential for attracting a carrier which selectively suppliesto one of said second gate electrodes an electrical potential forattracting said carrier toward one of said second gate insulators undersaid one of said second gate electrodes.
 14. The nonvolatile memory cellaccording to claim 12 wherein said first carrier-acceleration-injectionportion functions as a carrier path to supply carriers from said firstimpurity region to said carrier-supplying portion when said secondcarrier-acceleration-injection portion injects into said second one ofsaid second gate insulators carriers supplied from saidcarrier-supplying portion, and said secondcarrier-acceleration-injection portion functions as a carrier path tosupply carriers from said second impurity region to saidcarrier-supplying portion when said first carrier-acceleration-injectionportion injects into said first one of said second gate insulatorscarriers supplied from said carrier-supplying portion.
 15. Thenonvolatile memory cell according to claim 13 wherein said firstcarrier-acceleration-injection portion functions as a carrier path tosupply carriers from said first impurity region to saidcarrier-supplying portion when said secondcarrier-acceleration-injection portion injects into said second one ofsaid second gate insulators carriers supplied from saidcarrier-supplying portion, and wherein said secondcarrier-acceleration-injection portion functions as a carrier path tosupply carriers from said second impurity region to saidcarrier-supplying portion when said first carrier-acceleration-injectionportion injects into said first one of said second gate insulatorscarriers supplied from said carrier-supplying portion.
 16. Thenonvolatile memory cell according to claim 12 wherein an insulatingmaterial is formed at least on end surfaces of said one gate electrodeout of said first and second gate electrodes.
 17. The nonvolatile memorycell according to claim 16 wherein said insulating material formed onsaid end surfaces of said one gate electrode is of a sidewall insulatingmaterial left after anisotropically etching an insulating materialformed uniformly on said main surface of said substrate.
 18. Thenonvolatile memory cell according to claim 16 wherein said insulatingmaterial formed on said end surfaces of said one gate electrode is anoxide film formed by oxidizing said one gate electrode.
 19. Thenonvolatile memory cell according to claim 12 wherein an insulator isformed to insulate said first gate electrode and said second gateelectrodes from each other.
 20. The nonvolatile memory cell according toclaim 12 wherein said first one of said second gate electrodes and saidgate insulator thereof are extended to cover a top surface and an endsurface of one side of said first gate electrode, and said second one ofsaid second gate electrode and said gate insulator thereof are extendedto cover a top surface and an end surface of the other side of saidfirst gate electrode.
 21. The nonvolatile memory cell according to claim12 wherein said first gate electrode and said insulator thereof areextended to cover a top surface and an end surface of adjacent saidfirst one and said second one of said second gate electrodes.
 22. Thenonvolatile memory cell according to claim 2 wherein a step whosesidewall has a vertical component to a carrier-transport direction isformed in a surface of said carrier-acceleration-injection portion. 23.The nonvolatile memory cell according to claim 4 wherein a step whoseside wall has a vertical component to a carrier-transport direction isformed in a surface of said carrier-acceleration-injection portion 24.The nonvolatile memory cell according to claim 12 wherein a step whosesidewall has a vertical component to a carrier-transport direction isformed in a surface of said carrier-acceleration-injection portion. 25.The nonvolatile memory cell according to claim 2 wherein each said gateinsulator is of a three-layer structure including: a first layer comingin contact with said channel forming semiconductor region; a third layerin contact with said gate electrode; and a second layer between saidfirst layer and said third layer wherein a carrier tunnel probability ofsaid third layer is higher than a carrier tunnel probability of saidfirst layer.
 26. The nonvolatile memory cell according to claim 4wherein each said gate insulator is of a three-layer structureincluding: a first layer coming in contact with said channel formingsemiconductor region; a third layer in contact with said gate electrode;and a second layer between said first layer and said third layer whereina carrier tunnel probability of said third layer is higher than acarrier tunnel probability of said first layer.
 27. The nonvolatilememory cell according to claim 12 wherein each said gate insulator is ofa three-layer structure including: a first layer coming in contact withsaid channel forming, semiconductor region; a third layer in contactwith said gate electrode; and a second layer between said first layerand said third layer wherein a carrier tunnel probability of said thirdlayer is higher than a carrier tunnel probability of said first layer.28. The nonvolatile memory cell according to claim 2 wherein an impurityconcentration of said carrier-acceleration-injection portion is morethan 2×10¹⁷ atom/cm.
 29. The nonvolatile memory cell according to claim4 wherein an impurity concentration of saidcarrier-acceleration-injection portion is more than 2×10¹⁷ atom/cm. 30.The nonvolatile memory cell according to claim 12 wherein an impurityconcentration of said carrier-acceleration-injection portion is morethan 2×10¹⁷ atom/cm.
 31. The nonvolatile memory cell according to claim2 wherein a distance across said carrier-acceleration-injection portionin a direction connecting said first impurity region to said secondimpurity region is less than fourteen times the mean free path of a hotcarrier.
 32. The nonvolatile memory cell according to claim 4 wherein adistance across said carrier-acceleration-injection portion in adirection connecting said first impurity region to said second impurityregion is less than fourteen times the mean free path of a hot carrier.33. The nonvolatile memory cell according to claim 12 wherein a distanceacross said carrier-acceleration-injection portion in a directionconnecting said first impurity region to said second impurity region isless than fourteen times the mean free path of a hot carrier.
 34. Thenonvolatile memory cell according to claim 2 wherein saidacceleration-electrical potential forms a space charge region in saidcarrier-acceleration-injection portion from an adjacent said impurityregion to which said acceleration-electrical potential is supplied andenergy capable of getting over a potential barrier V_(B) formed at aninterface with said the carrier-acceleration-injection portion and saidgate insulator thereover is supplied to said carriers reached withinsaid space charge region.
 35. The nonvolatile memory cell according toclaim 4 wherein said acceleration-electrical potential forms a spacecharge region in said carrier-acceleration-injection portion from anadjacent said impurity region to which said acceleration-electricalpotential is supplied and energy capable of getting over a potentialbarrier V_(B) formed at an interface with said thecarrier-acceleration-injection portion and said gate insulator thereoveris supplied to said carriers reached within said space charge region.36. The nonvolatile memory cell according to claim 12 wherein saidacceleration-electrical potential forms a space charge region in saidcarrier-acceleration-injection portion from an adjacent said impurityregion to which said acceleration-electrical potential is supplied andenergy capable of getting over a potential barrier V_(B) formed at aninterface with said the carrier-acceleration-injection portion and saidgate insulator thereover is supplied to said carriers reached withinsaid space charge region.
 37. A method of programming the nonvolatilememory cell according to claim 2 comprising: a process to supply to saidsecond impurity region acceleration-electrical potential more thanV_(B)−2φ_(F2) :a Fermi-level in the carrier-acceleration-injectionportion) so that energy capable of getting over a potential barrierV_(B) to be formed at an interface with saidcarrier-acceleration-injection portion and said gate insulator thereovermay be supplied to said carrier concerned; a process to supply carriersfrom said first impurity region to said carrier-supplying portion insaid channel forming semiconductor region; and a process to move to saidcarrier-acceleration-injection portion carriers which are supplied tosaid carrier-supplying portion.
 38. A method of programming thenonvolatile memory cell according to claim 37 wherein said electricalpotential for attracting a carrier is more than V_(B)−φ_(GB) (φ_(GB): awork function difference between a gate electrode andcarrier-acceleration-injection portion).
 39. A method of programming thenonvolatile memory cell according to 37 wherein carriers are suppliedfrom one of said impurity regions to said carrier-supplying portion byforward-biasing said one of said impurity regions.
 40. A method ofprogramming the nonvolatile memory cell according to claim 37 wherein acarrier is supplied from one of said impurity regions to saidcarrier-supplying portion by inducing a channel in a surface of saidcarrier-supplying portion.
 41. A method of programming the nonvolatilememory cell according to claim 4 comprising: a process to supply to saidsecond impurity region acceleration-electrical potential more thanV_(B)−2φ_(F2) (φ_(F2): a Fermi-level in thecarrier-acceleration-injection portion) so that energy capable ofgetting over a potential barrier V_(B) to be formed at an interface withsaid carrier-acceleration-injection portion and said second gateinsulator may be supplied to said carrier concerned; a process to supplyelectrical potential for attracting carriers to said second gateelectrode; a process to supply carriers from said first impurity regionto said carrier-supplying portion in said channel forming semiconductorregion; and a process to move to said carrier-acceleration-injectionportion carriers supplied to said carrier-supplying portion.
 42. Amethod of programming the nonvolatile memory cell according to claim 41wherein said electrical potential for attracting a carrier is more thanV_(B)−φ_(GB) (φ_(GB): a work function difference between a gateelectrode and carrier-acceleration-injection portion).
 43. A method ofprogramming the nonvolatile memory cell according to claim 41 whereincarriers are supplied from one of said impurity regions to saidcarrier-supplying portion by forward-biasing said one of said impurityregions.
 44. A method of programming the nonvolatile memory cellaccording to claim 41 wherein a carrier is supplied from one of saidimpurity regions to said carrier-supplying portion by inducing a channelin a surface of said carrier-supplying portion.
 45. A method ofprogramming the nonvolatile memory cell according to claim 26 comprisingsteps of: supplying to said gate electrode electrical potential forinducing a channel which is larger than a gate threshold voltage of saidcorresponding gate; predetermining electrical potential of said firstimpurity region to a first electrical potential which is smaller thansaid acceleration-electrical potential and which is larger than a valueobtained by deducting said threshold voltage from said electricalpotential for inducing a channel; and changing electrical potential ofsaid first impurity region to said first electrical potential or asecond electrical potential less than said value obtained by deductingsaid gate threshold voltage from said electrical potential for inducinga channel to select programming information.
 46. A method of programmingthe nonvolatile memory cell according to claim 45 wherein saidelectrical potential for attracting a carrier is more than V_(B)−φ_(GB)(φ_(GB): a work function difference between a gate electrode andcarrier-acceleration-injection portion).
 47. A method of programming thenonvolatile memory cell according to claim 45 wherein carriers aresupplied from one of said impurity regions to said carrier-supplyingportion by forward-biasing said one of said impurity regions.
 48. Amethod of programming the nonvolatile memory cell according to claim 45wherein a carrier is supplied from one of said impurity regions to saidcarrier-supplying portion by inducing a channel in a surface of saidcarrier-supplying portion.
 49. A method of programming the nonvolatilememory cell according to claim 45 wherein said second electricalpotential is selected out of a plurality of levels of electricalpotential.
 50. A method of programming the nonvolatile memory cellaccording to claim 27 comprising steps of: supplying to said first gateelectrode electrical potential for inducing a channel which is largerthan a gate threshold voltage of said corresponding gate; predeterminingelectrical potential of said first impurity region to a first electricalpotential which is smaller than said acceleration-electrical potentialand which is larger than a value obtained by deducting said thresholdvoltage from said electrical potential for inducing a channel; andchanging electrical potential of said first impurity region to saidfirst electrical potential or a second electrical potential less thansaid value obtained by deducting said gate threshold voltage from saidelectrical potential for inducing a channel to select programminginformation.
 51. A method of programming the nonvolatile memory cellaccording to claim 50 wherein said electrical potential for attracting acarrier is more than V_(B)−φ_(GB) (φ_(GB): a work function differencebetween a gate electrode and carrier-acceleration-injection portion).52. A method of programming the nonvolatile memory cell according toclaim 50 wherein carriers are supplied from one of said impurity regionsto said carrier-supplying portion by forward-biasing said one of saidimpurity regions.
 53. A method of programming the nonvolatile memorycell according to claim 50 wherein a carrier is supplied from one ofsaid impurity regions to said carrier-supplying portion by inducing achannel in a surface of said carrier-supplying portion.
 54. A method ofprogramming the nonvolatile memory cell according to claim 50 whereinsaid second electrical potential is selected out of a plurality oflevels of electrical potential.
 55. A method of programming thenonvolatile memory cell according to claim 12 wherein carrier injectionfrom said second carrier-acceleration-injection portion into said secondone of said second gate insulators comprises: a process to supply tosaid second impurity region an acceleration-electrical potential morethan V_(B)−2φ_(F2) (φ_(F2): a Fermi-level in thecarrier-acceleration-injection-portion) so that energy capable ofgetting over a potential barrier VB to be formed at an interface withsaid first carrier-acceleration-injection portion and said second one ofsaid second gate insulators may be supplied to the carrier concerned; aprocess to supply electrical potential for attracting carriers to saidsecond one of said second gate electrodes; a process to supply carriersfrom said first impurity region to said carrier-supplying portionthrough said first carrier-acceleration-injection portion; and a processto move to said second carrier acceleration-injection-portion carrierssupplied to said carrier-supplying portion wherein carrier injectionfrom said first carrier-acceleration-injection portion into said firstone of said second gate insulators comprises: a process to supply tosaid first impurity region an acceleration-electrical potential morethan V_(B)−2φ_(F2) so that energy capable of overcoming an electricalpotential barrier V_(B) to be formed at an interface with said firstcarrier-acceleration-injection portion and said first one of said secondgate insulators may be supplied to said carrier concerned; a process tosupply electrical potential for attracting a carrier to said first oneof said second gate electrodes; a process to supply carriers from saidsecond impurity region to said carrier-supplying portion through saidsecond carrier-acceleration-injection portion; and a process to move tosaid first carrier-acceleration-injection portion carriers supplied tosaid carrier-supplying portion.
 56. A method of programming thenonvolatile memory cell according to claim 55 wherein carrier injectionfrom said second carrier-acceleration-injection portion to said secondone of said second gate insulators comprises steps of: supplying to saidfirst one of said second gate electrodes electrical potential which islarger than a gate threshold voltage; supplying to said first gateelectrode electrical potential for inducing a channel which is largerthan said gate threshold voltage; predetermining electrical potential ofsaid first impurity region to said first electrical potential which issmaller than said acceleration-electrical potential and which is largerthan said value obtained by deducting said threshold voltage from saidelectrical potential for inducing a channel; and changing electricalpotential of said first impurity region to said first electricalpotential or a second electrical potential less than said value which isobtained by deducting said gate threshold voltage from said electricpotential for inducing a channel to select programming informationwherein carrier injection from a first carrier-acceleration-injectionportion into said first one of said second gate insulators comprisessteps of: supplying to said second one of said second gate electrodeselectrical potential which is larger than said gate threshold voltage;supplying to said first gate electrode electrical potential for inducinga channel which is larger than said gate threshold voltage;predetermining electrical potential of said second impurity region tosaid first electrical potential which is smaller than saidacceleration-electrical potential and which is larger than said valueobtained by deducting said threshold voltage from said electricalpotential for inducing a channel; and changing electrical potential ofsaid second impurity region to said first electrical potential or secondelectrical potential less than said value obtained by deducting the gatethreshold voltage from said electrical potential for inducing a channelto select programming information.
 57. A method of programming thenonvolatile memory cell according to claim 56 wherein said electricalpotential for attracting a carrier is more than V_(B)−φ_(GB) (φ_(GB): awork function difference between a gate electrode andcarrier-acceleration-injection portion).
 58. A method of programming thenonvolatile memory cell according to claim 56 wherein carriers aresupplied from one of said impurity regions to said carrier-supplyingportion by forward-biasing said one of said impurity regions.
 59. Amethod of programming the nonvolatile memory cell according to claim 56wherein a carrier is supplied from one of said impurity regions to saidcarrier-supplying portion by inducing a channel in a surface of saidcarrier-supplying portion.
 60. A method of programming the nonvolatilememory cell according to claim 56 wherein said second electricalpotential is selected out of a plurality of levels of electricalpotential.
 61. A method of reading stored information in the nonvolatilememory cell according to claim 2 wherein supplied to said first impurityregion is reverse-biasing electrical potential which is smaller thanV_(B)−2φ_(F2) (V_(B): electrical potential barrier formed at theinterface with the gate insulator and carrier-acceleration-injectionportion; φ_(F2): Fermi-level of the carrier-acceleration-injectionportion) and which is larger than said electrical potential in saidsecond impurity region, and wherein supplied to said gate electrode todetect said electrical potential of said first impurity region is anelectrical potential which is larger than a maximum value of a pluralityof said programmed gate threshold voltages.
 62. A method of readingstored information in the nonvolatile memory cell according to claim 4wherein supplied to said first impurity region is reverse-biasingelectrical potential which is smaller than V_(B)−2φ_(F2) (V_(B):potential barrier formed at the interface with the second gate insulatorand carrier-acceleration-injection portion; φ_(F2): a Fermi-level of thecarrier-acceleration-injection portion) and which is larger than saidelectrical potential in said second impurity region, and wherein anelectrical potential which is larger than said gate threshold voltage issupplied to said first gate electrode, wherein an electrical potentialwhich is larger than a maximum value of a plurality of said programmedgate threshold voltages is supplied to said second gate electrode todetect said electrical potential of said first impurity region.
 63. Amethod of reading stored information from one of a pair of second gateinsulators in the nonvolatile memory cell according to claim 12 whereina reverse-biasing electrical potential is supplied to said one impurityregion out of said first and second impurity regions being further fromsaid one of said pair of second gate insulators from which informationis to be read than said other impurity region wherein saidreverse-biasing electrical potential is smaller than V_(B)−2φ_(F2)(V_(B): potential barrier formed at the interface with the second gateinsulator and carrier-acceleration-injection portion; φ_(F2): aFermi-level of the carrier-acceleration-injection portion) and is largerthan said electrical potential in said other impurity region; anelectrical potential which is larger than said gate threshold voltage issupplied to said first gate electrode; and an electrical potential whichis larger than a maximum value of a plurality of said programmed gatethreshold voltages is supplied to each of said first and second one ofsaid second gate electrode to detect the electrical potential of saidother impurity region.
 64. A nonvolatile memory array configured bydisposing in the form of a matrix the nonvolatile memory cells asclaimed in claim 2 comprising: a plurality of bit lines (L_(B)) each oneof which connects each of said first impurity regions of saidnonvolatile memory cells disposed on a same row; a plurality of commonlines (L_(C)) each one of which commonly connects each of said secondimpurity regions of a pair of said nonvolatile memory cells adjacent tothe direction of a column; and a plurality of word lines (L_(W)) eachone of which connects each of said gate electrodes of said nonvolatilememory cells disposed on a same column.
 65. A nonvolatile memory arrayconfigured by disposing in the form of a matrix the nonvolatile memorycells as claimed in claim 4 comprising: a plurality of bit lines (L_(B))each one of which connects each of said first impurity regions of saidnonvolatile memory cells disposed on a same row; a plurality of commonlines (L_(C)) each one of which commonly connects in the direction of acolumn each of said second impurity regions of a pair of nonvolatilememory cells adjacent to the direction of a row; a plurality of controllines (L_(S)) each one of which connects each of said second gateelectrodes in said nonvolatile memory cells disposed on a same column;and a plurality of word lines (L_(W)) each one of which connects each ofsaid first gate electrodes of said nonvolatile memory cells disposed ona same column.
 66. A nonvolatile memory array configured by disposing inthe form of a matrix the nonvolatile memory cells as claimed in claim 4comprising: a plurality of bit lines (L_(B)) each one of which connectseach of said first impurity regions of said nonvolatile memory cellsdisposed on a same row; a plurality of common lines (L_(C)) each one ofwhich commonly connects in the direction of a column each of said secondimpurity regions of a pair of nonvolatile memory cells adjacent to thedirection of a row; a plurality of control lines (L_(S)) each one ofwhich connects each of said second gate electrodes of said nonvolatilememory cells disposed on a same row; and a plurality of word lines(L_(W)) each one of which connects each of said first gate electrodes ofsaid nonvolatile memory cells disposed on a same column.
 67. Anonvolatile memory array configured by disposing in the form of a matrixthe nonvolatile memory cells as claimed in claim 4 comprising: aplurality of bit lines (L_(B)) each one of which connects each of saidsecond impurity regions of said nonvolatile memory cells disposed on asame row; a plurality of common lines (L_(C)) each one of which commonlyconnects in the direction of a column each of said first impurityregions of a pair of nonvolatile memory cells adjacent to the directionof a row; a plurality of control lines (L_(S)) each one of whichconnects each of said second gate electrodes of said nonvolatile memorycells disposed on a same row; and a plurality of word lines (L_(W)) eachone of which connects each of said first gate electrodes of saidnonvolatile memory cells disposed on a same row.
 68. A nonvolatilememory array configured by disposing in the form of a matrix thenonvolatile memory cells as claimed in claim 4 comprising: a pluralityof bit lines (L_(B)) each one of which connects each of said secondimpurity regions of said nonvolatile memory cell disposed on a same row;a plurality of common lines (L_(C)) each one of which commonly connectsin the direction of a column each of said first impurity regions of apair of nonvolatile memory cells adjacent to the direction of a row; aplurality of control lines (L_(S)) each one of which connects each ofsaid second gate electrodes of said nonvolatile memory cells disposed ona same row; and a plurality of word lines (L_(W)) each one of whichconnects each of said first gate electrodes of said nonvolatile memorycells disposed on a same column.
 69. A nonvolatile memory arrayconfigured by disposing in the form of a matrix the nonvolatile memorycell as claimed in claim 12 comprising: a plurality of bit lines (L_(B))each one of which commonly connects in the direction of a column each ofthe first and second impurity regions of a pair of nonvolatile memorycells adjacent to the direction of a row; a plurality of word lines(L_(W)) each one of which connects each of said first gate electrodes ofsaid nonvolatile memory cells disposed on a same row, a plurality offirst control lines (L_(SL)) each one of which connects each of saidfirst one of said second gate electrodes of said nonvolatile memorycells disposed on a same column; and a plurality of second control lines(L_(SR)) each one of which connects each of said second one of saidsecond gate electrodes of said nonvolatile memory cells disposed on asame column.
 70. A nonvolatile memory array configured by disposing inthe form of a matrix the nonvolatile memory cells as claimed in claim 12comprising: a plurality of common lines (L_(C)) each one of whichcommonly connects in the direction of a column each of said impurityregions at one side of a pair of nonvolatile memory cells adjacent tothe direction of a row; a plurality of bit lines (L_(B)) each one ofwhich connects each of said impurity regions at the other side of saidnonvolatile memory cells disposed on a same row; a plurality of wordlines (L_(W)) each one of which connects each of said first gateelectrodes of said nonvolatile memory cells disposed on a same column, aplurality of first control lines (L_(Sa)) each one of which connectseach of said first one of said second gate electrodes of saidnonvolatile memory cells disposed on a same column; and a plurality ofsecond control lines (L_(Sb)) each one of which connects each of saidsecond one of said second gate electrodes of said nonvolatile memorycells disposed on a same column.
 71. A method of programming anonvolatile memory cell wherein said nonvolatile memory cell comprises:first and second impurity regions of opposite conductivity type formedin a main surface of a substrate and separated therebetween by a channelforming semiconductor region of one conductivity type in said mainsurface of said substrate wherein a carrier-supplying portion isdisposed adjacent to said first impurity region and acarrier-acceleration-injection portion is disposed adjacent to saidsecond impurity region; and a gate electrode formed on a gate insulatoron said channel forming semiconductor region wherein said gate electrodeintegrally covers said carrier-supplying portion and saidcarrier-acceleration-injection portion; wherein said method ofprogramming said cell comprises the steps of: supplying to said secondimpurity region acceleration-electrical potential more thanV_(B)−2φ_(F2) (φ_(F2) :a Fermi-level in thecarrier-acceleration-injection portion) so that energy capable ofgetting over a potential barrier V_(B) to be formed at an interface withsaid carrier-acceleration-injection portion and said gate insulatorthereover may be supplied to said carrier concerned; supplying carriersfrom said first impurity region to said carrier-supplying portion insaid channel forming semiconductor region; and moving to saidcarrier-acceleration-injection portion carriers which are supplied tosaid carrier-supplying portion whereby carriers are injected and storedin a carrier trapping means of said gate insulator.
 72. A method ofreading stored information in a nonvolatile memory cell wherein saidnonvolatile memory cell comprises: first and second impurity regions ofopposite conductivity type formed in a main surface of a substrate andseparated therebetween by a channel forming semiconductor region of oneconductivity type in said main surface of said substrate wherein acarrier-supplying portion is disposed adjacent to said first impurityregion and a carrier-acceleration-injection portion is disposed adjacentto said second impurity region; and a gate electrode formed on a gateinsulator on said channel forming semiconductor region wherein said gateelectrode integrally covers said carrier-supplying portion and saidcarrier-acceleration-injection portion; wherein said method of readingstored information in said cell comprises the steps of: supplying tosaid first impurity region reverse-biasing electrical potential which issmaller than V_(B)−2φ_(F2) (V_(B): electrical potential barrier formedat the interface with the gate insulator andcarrier-acceleration-injection portion; φ_(F2): Fermi-level of thecarrier-acceleration-injection portion) and which is larger than saidelectrical potential in said second impurity region, and supplying tosaid gate electrode to detect said electrical potential of said firstimpurity region an electrical potential which is larger than a maximumvalue of a plurality of programmed gate threshold voltages.
 73. A methodof fabricating a nonvolatile memory cell comprising: forming a p-well ina semiconductor substrate; defining a channel forming semiconductorregion in a surface of said p-well wherein said channel formingsemiconductor region separates a first impurity region and a secondimpurity region; forming a carrier-supplying portion of said channelforming conductor region adjacent to said first impurity region; forminga carrier-acceleration-injection portion of said channel formingsemiconductor region adjacent to said second impurity region whereinsaid carrier-acceleration-injection portion and said carrier-supplyingportion are in contact with each other; forming a gate insulator on asurface of said substrate wherein said gate insulator covers eachopposite end surface of said first and second impurity regions andcovers said channel forming semiconductor region; and forming a gateelectrode overlying said gate insulator to complete fabrication of saidnonvoltile memory cell.
 74. The method according to claim 73 whereinsaid gate insulator comprises a three-layer structure.
 75. The methodaccording to claim 73 wherein said step of forming a gate electrodeoverlying said gate insulator comprises: forming a first gate electrodeoverlying said carrier-supplying portion; and forming a second gateelectrode overlying said carrier-acceleration-injection portion whereinsaid second gate electrode and a second gate insulator are extended tocover a top and end surface of said first gate electrode.
 76. A methodof fabricating a nonvolatile memory cell comprising: forming a p-well ina semiconductor substrate; defining a channel forming semiconductorregion in a surface of said p-well wherein said channel formingsemiconductor region separates a first impurity region and a secondimpurity region; forming a first carrier-acceleration-injection portionof said channel forming semiconductor region adjacent to said firstimpurity region; forming a second carrier-acceleration-injection portionof said channel forming semiconductor region adjacent to said secondimpurity region; forming a carrier-supplying portion of said channelforming conductor region between said first and secondcarrier-acceleration-injection portions; forming a gate insulator on asurface of said substrate wherein said gate insulator covers eachopposite end surface of said first and second impurity regions andcovers said channel forming semiconductor region; and forming a gateelectrode overlying said gate insulator to complete fabrication of saidnonvoltile memory cell.
 77. The nonvolatile memory cell according toclaim 2 wherein each said gate insulator is of a three-layer structureincluding: a first layer coming in contact with said channel formingsemiconductor region; a third layer in contact with said gate electrode;and a second layer between said first layer and said third layer whereina carrier tunnel probability of said first layer is higher than acarrier tunnel probability of said third layer.
 78. The nonvolatilememory according to claim 77 wherein the thickness of said first layeris made thinner that the thickness of said third layer.
 79. Thenonvolatile memory cell according to claim 4 wherein each said gateinsulator is of a three-layer structure including: a first layer comingin contact with said channel forming semiconductor region; a third layerin contact with said gate electrode; and a second layer between saidfirst layer and said third layer wherein a carrier tunnel probability ofsaid first layer is higher than a carrier tunnel probability of saidthird layer.
 80. The nonvolatile memory according to claim 79 whereinthe thickness of said first layer is made thinner that the thickness ofsaid third layer.
 81. The nonvolatile memory cell according to claim 12wherein each said gate insulator is of a three-layer structureincluding: a first layer coming in contact with said channel formingsemiconductor region; a third layer in contact with said gate electrode;and a second layer between said first layer and said third layer whereina carrier tunnel probability of said first layer is higher than acarrier tunnel probability of said third layer.
 82. The nonvolatilememory according to claim 81 wherein the thickness of said first layeris made thinner that the thickness of said third layer.